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Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
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Add a table of FPGA family with matching functions associated with
it and make all the code just look up the family in that table and
call the associated function instead of the horrible switch voodoo
which was duplicated all over the place.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
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Make the function return either 0 or -EINVAL, that is, normal
expected error codes and success codes instead of true/false
nonsense.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
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Move the function to the top of the file to avoid forward declaration.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
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Further improve the indentation in the rest of the file, where
the indentation is initially a bit less brutal. There is no
functional change in this patch.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
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Boldly go, where no programmer has gone before and just clean up
the indentation mayhem. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
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Clean up the printf() statements and get rid of the PRINTF()
macro by replacing it with debug_cond().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
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Most of the warnings seem to be related to using 'int' for size_t. Change
this and fix up the remaining warnings and problems. For bootm, the warning
was masked by others, and there is an actual bug in the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksize] <interface>
[<dev[:part]>] <filename>
Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Do not do partial bitstream detection based on bitstream
size and use bitstream_type argument which is passed
from the fpga core.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Use helper function zynq_validate_bitstream so that the
code can be reused easily for different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Use zynq_dma_xfer_init, zynq_align_dma_buffer,
zynq_dma_transfer helper function performing dma
transfers so that the code can be reused easily for
different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Warnings:
drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer
drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
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When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.
A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.
Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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- Descend into drivers/fpga/ only when CONFIG_FPGA=y
- Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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DMA doesn't work when src is placed below 1MB limit.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Buffers must be cache and dma aligned.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Some versions of the Zynq first stage boot loader enable PCAP loopback
during boot regardless of whether or not the boot image includes PL
configuration. This behavior only appears in certain boot modes (notably
QSPI boot). Attempting to configure the PL with the loopback bit set
will result in timeouts and will prevent successful configuration.
In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
than 1sec, hence increased the program time by 4sec to
sync' all soc's.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
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Ensure that wrong bitstream won't be loaded
to current device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
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Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.
The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
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All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
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In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
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CONFIG_FPGA in past was a bitfield where bits
were use for vendor identification.
This fix should be the part of this commit:
"Improve configuration of FPGA subsystem"
(sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
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No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
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'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
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Deassert the CONFIG pin before asserting it again. This assures that the
FPGA will be resetted and therefore configuration will be correctly
enabled.
This is also already done on other FPGA's, e.g. Stratix.
Signed-off-by: Stephan Gatzka <stephan.gatzka@hbm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Thomas Weber <weber@corscience.de>
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CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print
the current status of FPGA loading - an undef in the code made this
CONFIG_ useless.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Fix:
ivm_core.c: In function 'ispVMLCOUNT':
ivm_core.c:2105:16: warning: unused variable 'usByte'
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
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lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
3 has type 'const char *'
lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
4 has type 'long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
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The Lattice code was missed by commit e6a857d "fpga: constify to fix
build warning" resulting in such warnings:
fpga.c: In function 'fpga_load':
fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type
fpga.c: In function 'fpga_dump':
fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target type
Signed-off-by: Wolfgang Denk <wd@denx.de>
cc: Stefano Babic <sbabic@denx.de>
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Fix compiler warning:
cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type
Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
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Support FPGAs which use Fast Passive Parallel configuration
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
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Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Acked-by: Detlev Zundel <dzu@denx.de>
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Currently the hardware was left in an undefined state in case Spartan3
serial load failed. This patch adds Xilinx_abort_fn to give the board
a possibility to clean up in this case.
Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
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Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Commit 3b8ac464 "FPGA: add support for downloading Lattice bitstream"
added support for Lattice devices, but failed to add #ifdef's that are
needed when building for non-Lattice devices, which results in build
failures like these:
Configuring for GEN860T board...
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dev_info':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:145: undefined reference to `lattice_info'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dump':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:269: undefined reference to `lattice_dump'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_load':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:233: undefined reference to `lattice_load'
make: *** [u-boot] Error 1
Add the missing code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.
The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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