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As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
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The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
This meant that drivers which used fsl_phy_enet_if to deal with
PHY interfaces would have to convert between the two (or we would have
to have them mirror each other, and deal with the ensuing maintenance
headache). Instead, we switch all clients of fsl_phy_enet_if over to
phy_interface_t, which should become the standard, anyway.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Detlev Zundel <dzu@denx.de>
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Have a common enum for phy types that we use in the UCC driver. We will
also use this enum for dealing with phy connection fixup in the device
tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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There's no sensible reason to unite speed and interface type into
one variable. So split this variable enet_interface into two
vars: enet_interface_type, which hold the interface type and speed.
Also: add the possibility for switching between 10 and 100 MBit
interfaces on the fly, when running in FAST_ETH mode.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Headers should include headers containing prototypes and defines they
depend on, don't assume that they're included by somebody else.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The uec driver contains code to hard code configuration information for the uec
ethernet controllers. This patch creates an array of uec_info structures, which
are then parsed by the corresponding driver instance to determine configuration.
It also creates function uec_standard_init() to initialize all UEC interfaces
for 83xx and 85xx.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Rename riscRx/riscTx to risc_rx/risc_tx to comply with Codingstyle.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Change UEC phy interface from GMII to RGMII on MPC8568MDS board
Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed,
but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable.
Now both UEC1 and UEC2 can work properly under u-boot.
It is also in consistent with the kernel setting for 8568 UEC phy interface.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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PHY drivers will use it to setup software delay between RXD and RXC
signals.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
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