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2014-09-08esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macrosWang Huan
For LS102xA, the processor is in little-endian mode, while esdhc IP is in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE are added. So accessing ESDHC registers can be determined by ESDHC IP's endian mode. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-04-23driver: Add support of image load for MMC & SPI in SPLPrabhakar Kushwaha
Add support of loading image, binary for MMC and SPI during SPL boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-24mmc: Split mmc struct, rework mmc initialization (v2)Pantelis Antoniou
The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2013-08-20powerpc: mpc85xx: Support booting from SD Card with SPLYing Zhang
The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-04-14fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov
Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2013-04-03mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza
Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2012-10-16mxc: Fix SDHC multi-instance clockBenoît Thébaudeau
On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not suitable for the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). This patch fixes this issue by adding a configuration field for the SDHC input clock frequency. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Andy Fleming <afleming@gmail.com>
2012-09-01fsl_esdhc: Remove cache snooping for i.MXBenoît Thébaudeau
The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
2012-05-08mmc: fsl_esdhc: Poll until card is not busy anymoreDirk Behme
This patch imports parts of two patches from the Freescale U-Boot with the following commit messages: ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648 http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=e436525a70fe47623d346bc7d9f08f12ff8ad787 The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixes http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=a77c6fec8596891be96b2cdbc742c9824844b92a Removed delay of 10 ms before each command. There should not be a need to have this delay after the ENGR00156405 patch that polls until card is not busy anymore before proceeding to next cmd. This patch imports the polling part of both patches. The auto-clock gating code don't apply for i.MX6 as implemented in these two patches. SYSCTL_RSTA was defined twice. Remove one definition. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Andy Fleming <afleming@freescale.com> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de>
2011-04-10fsl_esdhc: Deal with watermark level register related changesPriyanka Jain
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-24ppc/85xx: PIO Support for FSL eSDHC Controller DriverDipen Dudhat
On some Freescale SoC Internal DMA of eSDHC controller has bug. So PIO Mode has been introduced to do data transfer using CPU. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
2010-04-07fsl_esdhc: Only modify the field we are changing in WMLRoy Zang
When we set the read or write watermark in WML we should maintain the rest of the register as is, rather than using some hard coded value. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-07fsl_esdhc: Add function to reset the eSDHC controllerJerry Huang
To support multiple block read command we must set abort or use auto CMD12. If we booted from eSDHC controller neither of these are used and thus we need to reset the controller to allow multiple block read to function. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-07fsl_esdhc: Always stop clock before changing frequencyKumar Gala
We need to stop the clocks on 83xx/85xx as well as imx. No need to make this code conditional to just imx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefano Babic <sbabic@denx.de>
2010-03-07fsl_esdhc: add support for mx51 processorStefano Babic
The esdhc controller in the mx51 processor is quite the same as the one in some powerpc processors (MPC83xx, MPC85xx). This patches adapts the driver to support the arm mx51. Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-01-26fsl_esdhc: fix wrong clock maskLi Yang
Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS. Signed-off-by: Jin Qing <B24347@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-16fsl_esdhc: Add device tree fixupsAnton Vorontsov
This patch implements fdt_fixup_esdhc() function that is used to fixup the device tree. The function adds status = "disabled" propery if esdhc pins muxed away, otherwise it fixups clock-frequency for esdhc nodes. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-17Add support for the Freescale eSDHC found on 8379 and 8536 SoCsAndy Fleming
This uses the new MMC framework Some contributions by Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>