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2015-12-20arm: socfpga: de0_nano: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut
This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20arm: socfpga: cyclone5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut
This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut
This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20arm: socfpga: Allow DWC2 UDC probing from OFMarek Vasut
The USB gadget framework does not support DM yet, so add this bit to let DWC2 UDC probe from OF on platforms which support it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20arm: socfpga: socrates: Remove Micrel PHY configurationMarek Vasut
The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20arm: socfpga: sockit: Remove Micrel PHY configurationMarek Vasut
The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20arm: socfpga: de0_nano: Remove Micrel PHY configurationMarek Vasut
The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20arm: socfpga: cyclone5-socdk: Remove Micrel PHY configurationMarek Vasut
The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20arm: socfpga: arria5-socdk: Remove Micrel PHY configurationMarek Vasut
The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-18Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini
2015-12-18microblaze: Do not handle watchdog and gpio in SPLMichal Simek
watchdog and gpio are not validated for SPL that's why do not use them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18microblaze: Remove support for LL_TEMACMichal Simek
LL_TEMAC is available at big endian MB and it is not properly tested that's why the patch removes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18microblaze: Use malloc setting via KconfigMichal Simek
Clean board specific file. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-18microblaze: Make room for malloc before ELFMichal Simek
Create space below u-boot binary for early malloc. It means memory layout is stack grows down, space for early malloc, u-boot code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18net: gem: Add driver dependencies to PHYLIBMichal Simek
Clear driver dependecies via Kconfig. Remove PHYLIB dependency from the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18arm: zynq: Update ZYBO config optionsNathan Rossi
Update the ZYBO device tree and enable config options that relate to the added devices in the device tree. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2015-12-17usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.hMarek Vasut
The driver is actually for the Designware DWC2 controller. This patch renames the global s3c_udc.h header to dwc2_udc.h. The rename is done automatically: $ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \ `git grep "s3c_udc\.h" | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17usb: s3c-otg: Rename s3c_udc_probe() functionMarek Vasut
The driver is actually for the Designware DWC2 controller. This patch is the second and final to rename global symbol, the s3c_udc_probe() function. The rename is done automatically: $ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \ `git grep s3c_udc_probe | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17usb: s3c-otg: Rename struct s3c_plat_otg_dataMarek Vasut
The driver is actually for the Designware DWC2 controller. This patch is the first to rename global symbol, the struct s3c_plat_otg_data. The rename is done automatically: $ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \ `git grep s3c_plat_otg_data | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*Marek Vasut
The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the config option to make it less misleading. No functional change, just a mechanical change done using the following script: git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \ while read line ; do sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ; done Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17usb: s3c-otg: Tweak the commentsMarek Vasut
The driver is actually for the Designware DWC2 controller. Tweak the comments in the driver to reflect this fact. Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17usb: s3c-otg: Zap useless externsMarek Vasut
The extern statements are useless, remove them. Also remove the extern ... controller, which is completely useless. Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17usb: s3c-otg: Split private bits from s3c_udc.hMarek Vasut
Most of the functions are local to the s3c_udc driver, remove them from the s3c_udc.h header to stop those bits from propagating all over the place. Instead, move all the private stuff into new private s3c_udc_otg_priv.h header. Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17usb: s3c-otg: Rename struct s3c_udc to dwc2_udcMarek Vasut
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_udc to struct dwc2_udc to make things more obvious and clear. Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-16Merge git://git.denx.de/u-boot-rockchipTom Rini
2015-12-16Revert "include/linux: move typdef for uintptr_t"York Sun
This reverts commit e8f954a756a825130d11b9c8fca70101dd8b3ac5, which causes compiling errors on 32-bit hosts. Acked-by: Aneesh Bansal <aneesh.bansal@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
2015-12-15armv8: Add sata support on Layerscape ARMv8 boardTang Yuantian
Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal
LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15include/linux: move typdef for uintptr_tAneesh Bansal
uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. The typdef has been moved from include/compiler.h to include/linux/types.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15armv8: fsl-layerscale: Rewrite reserving memory for MC and debug serverYork Sun
MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15Reserve secure memoryYork Sun
Secure memory is at the end of memory, separated and reserved from OS, tracked by gd->secure_ram. Secure memory can host MMU tables, security monitor, etc. This is different from PRAM used to reserve private memory. PRAM offers memory at the top of u-boot memory, not necessarily the real end of memory for systems with very large DDR. Using the end of memory simplifies MMU setup and avoid memory fragmentation. "bdinfo" command shows gd->secure_ram value if this memory is marked as secured. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-14rockchip: Add basic support for kylin boardhuang lin
kylin board use rk3036 SOC, 512M sdram, 8G emmc. This add some basic files required to allow the board to output serial message and can run command(mmc info etc). Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-14Enable console log from earlyconsole in Linux bootargsPratiyush Mohan Srivastava
Remove 115200 from "earlycon" to avoid loss of initial log messages during linux kernel 4.1 bootup Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-14armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie
This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-14fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-14fsl/errata: move fsl_errata.h to common directoryShengzhou Liu
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-14driver/ddr/fsl: Update DDR4 RTT valuesYork Sun
DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-12stm32: Convert serial driver to DMKamil Lulko
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-11Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2015-12-11imx: mx7dsabresd: Add QSPI supportPeng Fan
Support qspi flashes for mx7dsabresd 1. introduce pin mux settings 2. enable qspi clock 3. introduce related macro definitions Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9: " QSPI signals are muxed with EPDC_D[7:0] When using QSPI: de-populate R388-R391, R396-R399 populate R392-R395, R299, R300 " After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info: " => sf probe SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Read: OK => sf erase 0 0x4000000 SF: 67108864 bytes @ 0x0 Erased: OK => sf write 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Written: OK " Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-12-10sunxi: power: enabled support for axp818vishnupatekar
Enabled support for AXP818 in SPL and u-boot. DCDC1, DCDC2, DCDC3 and DCSC5 are enabled. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: power: axp818: add support for axp818 drivervishnupatekar
AXP818 is rsb based PMIC and used on Allwinner A83T H8 Homlet dev board. It's registers are different and calculating reg config is different than that of earlier axp power ICs. DCDC1, DCDC2, DCDC3 and DCDC5 is implemented at the moment. all other voltages can be added subsequently. AXP datasheet is uploaded to wiki: http://linux-sunxi.org/File:AXP818_datasheet_Revision1.0.pdf Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add Machine Support for A83T SOCvishnupatekar
Allwinner A83T is octa-core cortex-a7 SOC. This enables support for A83T. SMP is not yet supported. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-09x86: Clean up ivybridge/chrome Kconfig optionsBin Meng
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-07CONFIG_NEEDS_MANUAL_RELOC: Fix warnings when not setTom Rini
Now that we may compile (but not link) code calling fixup_cmdtable when this is not set, we need to always have the declaration available. We should also make sure that anyone calling the function includes <command.h> as that's where the function declaration is. Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-07Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini
2015-12-07ARM: zynq: Extend malloc sizeMichal Simek
SPL DM MMC FAT requires more malloc space(3k fat buffers + dm) that it is available now. Extend SPL malloc space. Current OCM layout: 0xffff0000 - 0xfff2000 - Full malloc space 0xffff2000 - 0xffff300 - Stack location 0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space 0xfffffd00 - sizeof(GD) - GD 0xfffffe00 - 0xffffffff - SoC specific boot code Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07ARM: zynq: Fix location of stack and malloc areasMichal Simek
The patch "board_init: Change the logic to setup malloc_base" (sha1: 9ac4fc82071ce346e3885118242ff45d22f69b82) breaks SPL for Zynq because it puts early alloc area on the stack which caused that stack was decreased by CONFIG_SYS_MALLOC_F_LEN (0x400) and there was not enough space for regular stack. This patch changes memory layout to better utilize the last 64k OCM block. 0xffff0000 - 0xfff1000 - Full malloc space 0xffff1000 - 0xffff300 - Stack location 0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space 0xfffffd00 - sizeof(GD) - GD 0xfffffe00 - 0xffffffff - SoC specific boot code Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Moritz Fischer <moritz.fischer@ettus.com>