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2009-10-27ppc/85xx: Fix compiler warning in nand_spl/.../p1_p2_rdb/nand_boot.cKumar Gala
nand_boot.c: In function 'board_init_f': nand_boot.c:44: warning: 'sys_clk' may be used uninitialized in this function Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27ppc/85xx: Fix building NAND_SPL out of treeKumar Gala
We need to source files to exist in the O=<FOO> nand_spl dir when we build out of tree. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16ppc/P1_P2_RDB: NAND Boot SupportDipen Dudhat
NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2009-09-30NAND boot: MPC8536DS supportMingkai Hu
MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-28ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-11ppc4xx: Big cleanup of PPC4xx definesStefan Roese
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
2009-08-21Fix all linker scripts for older binutils versions (pre-2.16)Wolfgang Denk
Commit f62fb99941c6 fixed handling of all rodata sections by using a wildcard combined with calls to ld's builtin functions SORT_BY_ALIGNMENT() and SORT_BY_NAME(). Unfortunately these functions were only introduced with biunutils version 2.16, so the modification broke building with all tool chains using older binutils. This patch makes it work again. This is done by omitting the use of these functions for such old tool chains. This will result in slightly larger target binaries, as the rodata sections are no longer in optimal order alignment-wise which reauls in unused gaps, but the effect was found to be insignificant - especially compared to the fact that you cannot build U-Boot at all in the current state. As ld seems to have no support for conditionals we run the linker script through the C preprocessor which can be easily used to remove the unwanted function calls. Note that the C preprocessor must be run with the "-ansi" (or a "-std=") option to make sure all the system-specific predefined macros outside the reserved namespace are suppressed. Otherise, cpp might for example substitute "powerpc" to "1", thus corrupting for example "OUTPUT_ARCH(powerpc)" etc. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org>
2009-07-30ppc4xx: Canyonlands-NAND-boot: Support 2 Crucial 512MByte SODIMM'sStefan Roese
Some Canyonlands boards are equipped with different SODIMM's. This is no problem with the "normal" NOR booting Canyonlands U-Boot, since it automatically detects the SODIMM's via SPD data and correctly configures them. But the NAND booting version is different. Here we only have 4k of image size to completely setup the hardware, including DDR2 setup. So we need to use a fixed DDR2 setup here. This doesn't work for different SODIMM's right now. Currently only this Crucial SODIMM is support: CT6464AC667.8FB (dual ranked) Now some boards are shipped with this SODIMM: CT6464AC667.4FE (single ranked) This patch now supports both SODIMM's by configuring first for the dual ranked DIMM. A quick shows, if this module is really installed. If this test fails, the DDR2 controller is re-configured for the single ranked SODIMM. Tested with those SODIMM's: CT6464AC667.8FB (dual ranked) CT6464AC667.4FE (single ranked) Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-16nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directoryStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-07-06MX31: Add NAND SPL boot support to i.MX31 PDK board.Magnus Lilja
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2009-05-15Fix e-mail address of Gary Jennejohn.Detlev Zundel
Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-03-20Fix all linker script to handle all rodata sectionsTrent Piepho
A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
2009-03-09SIMPC8313 board: fix out of tree building.Wolfgang Denk
Fix typo in makefile which broke out of tree builds. Also use expolicit "rm" instead of "ln -sf" which is known to be unreliable. Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-28mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 buildKim Phillips
extend commit c70564e6b1bd08f3230182392238907f3531a87e "NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency to the simpc8313 build and fix this: ...Large Page NAND...Configuring for SIMPC8313 board... nand_boot_fsl_elbc.o: In function `nand_boot': nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache' make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1 make: *** [nand_spl] Error 2 Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-23Merge branch 'next'Kim Phillips
2009-01-23mpc83xx: New board support for SIMPC8313Ron Madrid
This patch will create a new board, SIMPC8313, from Sheldon Instruments. This board boots from NAND devices and is configureable for either large or small page devices. The board supports non-soldered DDR2, one ethernet port, a Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected to the eLBC providing glue logic to a TMS320C67xx DSP. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-23NAND: Fix cache and memory inconsistency issueDave Liu
We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-11-18Align end of bss by 4 bytesSelvamuthukumar
Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-30ARM: Add support for S3C6400 based SMDK6400 boardGuennadi Liakhovetski
SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl driver for it too. The board can also boot from the NOR flash, but due to hardware limitations it can only address 64KiB on it, which is not enough for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-08-12NAND boot: MPC8313ERDB supportScott Wood
Note that with older board revisions, NAND boot may only work after a power-on reset, and not after a warm reset. I don't have a newer board to test on; if you have a board with a 33MHz crystal, please let me know if it works after a warm reset. Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-07-29NAND: $(obj)-qualify ecc.h in kilauea NAND boot Makefile.Scott Wood
This fixes building out-of-tree. Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-06-12Change initdram() return type to phys_size_tBecky Bruce
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-04ppc4xx: Fix problem with SDRAM init in bamboo NAND booting portStefan Roese
This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene) introduced by the commit: ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S With this patch SDRAM will get initialized again and booting from NAND is working again. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
2008-06-03Remove shell variable UNDEF_SYM.Kenneth Johansson
UNDEF_SYM is a shell variable in the main Makefile used to force the linker to add all u-boot commands to the final image. It has no use here. Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
2008-06-03ppc4xx: Change Kilauea to use the common DDR2 init functionStefan Roese
This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-14ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand buildStefan Roese
Canyonlands has a file ddr2_fixed.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-30ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM moduleStefan Roese
This patch changes the Canyonlands/Glacier fixed DDR2 controller setup used for NAND booting to match the values needed for the new 512MB DIMM modules shipped with the productions boards: Crucial: CT6464AC667.8FB Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18ppc4xx: Change Canyonlands to support booting from 2k page NAND devicesStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18ppc4xx: Adjust Canyonlands fixed DDR2 setup (NAND booting) to 512MB SODIMMStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15ppc4xx: Add Canyonlands NAND booting supportStefan Roese
460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-12Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk
With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-09fix comments with new drivers organizationMarcel Ziswiler
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2008-01-04ppc4xx: Fix Sequoia NAND booting targetStefan Roese
The Sequoia NAND booting target now uses the recently extracted cpu/ppc4xx/denali_data_eye.c file too. Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-28ppc4xx: Fix compilation problem of kilauea/haleakala nand booting targetStefan Roese
Use correct link to nand_ecc now located in drivers/mtd/nand/ for the platforms mentioned above. Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-11Merge commit 'u-boot/master' into for-1.3.1Stefan Roese
Conflicts: drivers/rtc/Makefile
2007-11-25drivers/mtd : move mtd drivers to drivers/mtdJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-11-03ppc4xx: Add AMCC Kilauea/Haleakala NAND booting supportStefan Roese
This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Fix acadia_nand build problemStefan Roese
Since the cache handling functions were moved from start.S into cache.S the acadia NAND booting Makfile needs to be adapted accordingly. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAMEugene O'Brien
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: Note: As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM modules are still plugged in. So it is recommended to remove the DIMM modules while using the NAND booting code with the fixed SDRAM setup! Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
2007-09-11[ppc4xx] Individual handling of sdram.c for bamboo_nand buildGrzegorz Bernacki
Bamboo has a file sdram.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-06-19[ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese
The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-06ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese
This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese
2007-06-01ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese
This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-05ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06[PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese
As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05[PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>