blob: 8adcc4b3c39affae68163276339fc93b9c824d6e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
|
/*
* Copyright 2020 Scalys B.V.
* opensource@scalys.com
*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#include "dragonfruit.h"
void pci_init_board(void)
{
int serdes_config;
uint32_t boot_source;
ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;
uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
uint32_t regval;
/* SERDES configuration is determined boot time through the RCW config.
* It is located in the fourth RCW word (bit 128-135 of the RCW). */
serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
/* Configure SERDES lane multiplexing on Dragonfruit carrier */
scalys_carrier_setup_muxing(serdes_config);
#if 0
/* Dragonfruit Carrier board 1.x */
/*
* IRQ[0-3] : PCIe present detect signals
* IRQ[0] : SLOT1_PRSNT2_N : XXX
* IRQ[1] : SLOT2_PRSNT2_N : XXX
* IRQ[2] : SLOT3_PRSNT2_N : XXX
* IRQ[3] : SLOT4_PRSNT2_N : XXX
*
* Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7
* IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N
* IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N
* IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N
* IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N
*/
/* Set output to 0 to enable reference clocks */
regval = in_be32(gpio1_gpdat);
regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
out_be32(gpio1_gpdat, regval);
/* Set Enable outputs*/
regval = in_be32(gpio1_gpdir);
regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
out_be32(gpio1_gpdir, regval);
#else
/* Dragonfruit Carrier board 2.x/3.x */
/*
* PCIe present detect signals:
* IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
* IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
* IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
* IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
*
* Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7
* IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots)
* IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL
*/
/* Set output to 0 to enable reference clocks */
regval = in_be32(gpio1_gpdat);
regval &= ~( 0x80000000 >> 12 );
out_be32(gpio1_gpdat, regval);
/* Set Enable outputs */
regval = in_be32(gpio1_gpdir);
regval |= ( 0x80000000 >> 12 );
out_be32(gpio1_gpdir, regval);
/* Set PEX_REFCLK_SEL to 0 to select CLK0 */
/* Set IFC_PAR1 to output mode */
regval = in_be32(gpio2_gpdir);
regval |= ( 0x80000000 >> 14 );
out_be32(gpio2_gpdir, regval);
/* Set output to 0 to select clock source 0 */
regval = in_be32(gpio2_gpdat);
regval &= ~( 0x80000000 >> 14 );
out_be32(gpio2_gpdat, regval);
#endif
/*
* IFC_PAR0 : GPIO2_13 : PEX_PERST_N
*/
/* Remove reset from PCIe devices */
/* Set IFC_PAR0 to output mode */
regval = in_be32(gpio2_gpdir);
regval |= ( 0x80000000 >> 13 );
out_be32(gpio2_gpdir, regval);
/* Set output to 1 to clear reset */
regval = in_be32(gpio2_gpdat);
regval |= ( 0x80000000 >> 13 );
out_be32(gpio2_gpdat, regval);
/* Wait for 100 ms to allow the PCIe device to become ready */
mdelay(100);
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
|
