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/*
* Copyright 2017 Scalys B.V.
* opensource@scalys.com
*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#include <asm-generic/gpio.h>
#include "dragonfruit.h"
#define SLOT1_REFCLK_OE_N MPC85XX_GPIO_NR(1, 9)
#define SLOT2_REFCLK_OE_N MPC85XX_GPIO_NR(1, 10)
#define SLOT3_REFCLK_OE_N MPC85XX_GPIO_NR(1, 11)
#define SLOT4_REFCLK_OE_N MPC85XX_GPIO_NR(1, 12)
#define SLOT1_PRSNT2_N MPC85XX_GPIO_NR(1, 23)
#define SLOT2_PRSNT2_N MPC85XX_GPIO_NR(1, 24)
#define SLOT3_PRSNT2_N MPC85XX_GPIO_NR(1, 25)
#define SLOT4_PRSNT2_N MPC85XX_GPIO_NR(1, 30)
#define PEX_REFCLK_SEL MPC85XX_GPIO_NR(2, 14)
#define PEX_PERST_N MPC85XX_GPIO_NR(2, 13)
void pci_init_board(void)
{
int ret = 0;
int serdes_config;
ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* SERDES configuration is determined boot time through the RCW config.
* It is located in the fourth RCW word (bit 128-135 of the RCW). */
serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
scalys_carrier_setup_muxing(serdes_config);
ret += gpio_request(SLOT4_REFCLK_OE_N, "c19");
ret += gpio_request(PEX_REFCLK_SEL, "c14");
ret += gpio_request(PEX_PERST_N, "c15");
if (ret != 0)
printf("A gpio request failed(%i)\n", ret);
#if 0
/* Dragonfruit Carrier board 1.x */
/*
* IRQ[0-3] : PCIe present detect signals
* IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
* IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
* IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
* IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
*
* Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7
* IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N
* IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N
* IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N
* IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N
*/
/* Set output to 0 to enable reference clocks */
regval = in_be32(gpio1_gpdat);
regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
out_be32(gpio1_gpdat, regval);
/* Set Enable outputs*/
regval = in_be32(gpio1_gpdir);
regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
out_be32(gpio1_gpdir, regval);
#else
/* Dragonfruit Carrier board 2.x */
/*
* PCIe present detect signals:
* IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
* IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
* IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
* IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
*
* Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7
* IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots)
* IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL
*/
/* Set output to 0 to enable reference clocks */
gpio_direction_output(SLOT4_REFCLK_OE_N, 0);
/* Set PEX_REFCLK_SEL to 0 to select CLK0 */
gpio_direction_output(PEX_REFCLK_SEL, 0);
#endif
/*
* IFC_PAR0 : GPIO2_13 : PEX_PERST_N
*/
/* Remove reset from PCIe devices */
gpio_direction_output(PEX_PERST_N, 1);
/* Wait for 100 ms to allow the PCIe device to become ready */
mdelay(100);
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
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