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#PBL preamble and RCW header
AA55AA55 010E0100
#
## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (1800MHz speedgrade)
## DDR:1600MT/s
# 0c06000e 12000000 00000000 40000000
# 6c000002 40004000 e8105000 41000000
# 00000000 cafebabe 00000000 00030ffc
# 00000314 80000009 00000000 00000004
## SYS_CLK: 100MHz PLAT:600MHz Core:1500MHz FMAN: 700MHz (1533MHz speedgrade)
## DDR:1600MT/s
# 0c06000e 0f000000 00000000 40000000
# bc000002 40004000 e8105000 41000000
# 00000000 cafebabe 00000000 00030ffc
# 00000314 80000009 00000000 00000004
### lowest valid clock & pll settings
# 0806000a 0a000000 00000000 20000000
# bc000002 40004000 e8105000 61000000
# 00000000 cafebabe 00000000 00030ffc
# 00000314 80000009 00000000 00000004
## PCI SATA + Virtualization demo
# 0c06000e 12000000 00000000 40000000
# aa000002 40004000 e8105000 41000000
# 00000000 cafebabe 00000000 00030ffc
# 00000314 80000009 00000000 00000004
## SERDES PLL2 disabled
0c06000e 12000000 00000000 40000000
aa000002 00404000 e8105000 41000000
00000000 cafebabe 00000000 00030ffc
00000314 80000009 00000000 00000004
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