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| author | Wang Dongsheng <dongsheng.wang@freescale.com> | 2013-09-17 08:59:49 (GMT) |
|---|---|---|
| committer | Rivera Jose-B46482 <German.Rivera@freescale.com> | 2013-09-17 20:21:08 (GMT) |
| commit | 4b2b581bf100ab45e2c116fd08a9b94840ce3ebf (patch) | |
| tree | b0e9a42bb956c3f23d822990350c970a7235f18d | |
| parent | 9af64af96d4b6a79e08b7d082c168ded11f742b9 (diff) | |
| download | linux-fsl-qoriq-4b2b581bf100ab45e2c116fd08a9b94840ce3ebf.tar.xz | |
fsl/powerpc: fix kernel cannot boot under topaz
when we have embedded hypervisor functionality, the MMUCFG[LPIDSIZE]
is not zero, this is issue will occur.
asm functions (setup_altivec_idle + setup_pw20_idle) that overwrite
register r4. Register r4 holds the second parameter of the
setup___setup_cpu_e* functions and is a pointer to the cpu spec features.
Under baremetal the param is not used so the problem doesn't show up,
but under hypervisor it is used.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Tested-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Change-Id: I0fe5f7814ff0a77988f3b8540933a522f3217679
Reviewed-on: http://git.am.freescale.net:8181/4789
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Tudor Laurentiu-B10716 <Laurentiu.Tudor@freescale.com>
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
| -rw-r--r-- | arch/powerpc/kernel/cpu_setup_fsl_booke.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index acba3dfd..c39bbfb 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -59,15 +59,15 @@ _GLOBAL(has_pw20_altivec_idle) /* PW20 & AltiVec idle feature only exists for E6500 */ mfspr r0, SPRN_PVR - rlwinm r4, r0, 16, 16, 31 + rlwinm r11, r0, 16, 16, 31 lis r12, 0 ori r12, r12, PVR_VER_E6500@l - cmpw r4, r12 + cmpw r11, r12 bne 2f /* Fix erratum, e6500 rev1 does not support PW20 & AltiVec idle */ - rlwinm r4, r0, 0, 16, 31 - cmpwi r4, 0x20 + rlwinm r11, r0, 0, 16, 31 + cmpwi r11, 0x20 blt 2f li r3, 1 2: @@ -89,10 +89,10 @@ _GLOBAL(setup_pw20_idle) /* Set PW20_WAIT bit, enable pw20 state*/ ori r3, r3, PWRMGTCR0_PW20_WAIT - li r4, PW20_WAIT_IDLE_BIT + li r11, PW20_WAIT_IDLE_BIT /* Set Automatic PW20 Core Idle Count */ - rlwimi r3, r4, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT + rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT mtspr SPRN_PWRMGTCR0, r3 2: @@ -114,10 +114,10 @@ _GLOBAL(setup_altivec_idle) /* Enable Altivec Idle */ oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h - li r4, AV_WAIT_IDLE_BIT + li r11, AV_WAIT_IDLE_BIT /* Set Automatic AltiVec Idle Count */ - rlwimi r3, r4, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT + rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT mtspr SPRN_PWRMGTCR0, r3 2: |