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author | Ingo Molnar <mingo@elte.hu> | 2012-02-07 08:59:29 (GMT) |
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committer | Ingo Molnar <mingo@elte.hu> | 2012-02-07 08:59:29 (GMT) |
commit | 290436c9c61ac983b1bd425da67242a4357c7701 (patch) | |
tree | 35e1f189b62eb50515600ad607d7fb57fc547870 /arch/arm/mach-at91/at91sam9g45_reset.S | |
parent | 623ec991ce0e8cd5791bad656c162fa837635907 (diff) | |
parent | 62aa2b537c6f5957afd98e29f96897419ed5ebab (diff) | |
download | linux-fsl-qoriq-290436c9c61ac983b1bd425da67242a4357c7701.tar.xz |
Merge tag 'v3.3-rc2' into perf/core
Linux 3.3-rc2
Pick up the latest fixes.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mach-at91/at91sam9g45_reset.S')
-rw-r--r-- | arch/arm/mach-at91/at91sam9g45_reset.S | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S new file mode 100644 index 0000000..0468be1 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9g45_reset.S @@ -0,0 +1,40 @@ +/* + * reset AT91SAM9G45 as per errata + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> + * + * unless the SDRAM is cleanly shutdown before we hit the + * reset register it can be left driving the data bus and + * killing the chance of a subsequent boot from NAND + * + * GPLv2 Only + */ + +#include <linux/linkage.h> +#include <mach/hardware.h> +#include <mach/at91sam9_ddrsdr.h> +#include <mach/at91_rstc.h> + + .arm + + .globl at91sam9g45_restart + +at91sam9g45_restart: + ldr r0, .at91_va_base_sdramc0 @ preload constants + ldr r1, =at91_rstc_base + ldr r1, [r1] + + mov r2, #1 + mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN + ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST + + .balign 32 @ align to cache line + + str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access + str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 + str r4, [r1, #AT91_RSTC_CR] @ reset processor + + b . + +.at91_va_base_sdramc0: + .word AT91_VA_BASE_SYS + AT91_DDRSDRC0 |