diff options
author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2012-01-09 05:35:11 (GMT) |
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committer | Olof Johansson <olof@lixom.net> | 2012-02-06 17:16:15 (GMT) |
commit | 4fccf75ba3bee0bb3be7828caa03625d4ac100a2 (patch) | |
tree | ac2445c017187a1f68fbf642c1712706c0903c0b /arch/arm/mach-tegra/clock.c | |
parent | caa4868ee07029e60450909960652b96a50ebfbd (diff) | |
download | linux-fsl-qoriq-4fccf75ba3bee0bb3be7828caa03625d4ac100a2.tar.xz |
ARM: tegra: add support for new clock framework features
Add support for new clock framework features implemented in tegra30.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/clock.c')
-rw-r--r-- | arch/arm/mach-tegra/clock.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 8337068..8dad8d1 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -399,6 +399,28 @@ void tegra_periph_reset_assert(struct clk *c) } EXPORT_SYMBOL(tegra_periph_reset_assert); +/* Several extended clock configuration bits (e.g., clock routing, clock + * phase control) are included in PLL and peripheral clock source + * registers. */ +int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) +{ + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&c->spinlock, flags); + + if (!c->ops || !c->ops->clk_cfg_ex) { + ret = -ENOSYS; + goto out; + } + ret = c->ops->clk_cfg_ex(c, p, setting); + +out: + spin_unlock_irqrestore(&c->spinlock, flags); + + return ret; +} + #ifdef CONFIG_DEBUG_FS static int __clk_lock_all_spinlocks(void) |