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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-13 00:25:35 (GMT) |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-13 00:25:35 (GMT) |
| commit | 9219a3b9889dbc7dae68e472f239672ff48860b0 (patch) | |
| tree | c6446d63dd7ffb0f118804e354eee3d80041717e /arch/mips/include/asm/mipsregs.h | |
| parent | 23ead7291269db3be71b442324381c8d63e5d0b3 (diff) | |
| parent | cde15b5927fea3e1b4de0b277008cf273d8b000b (diff) | |
| download | linux-fsl-qoriq-9219a3b9889dbc7dae68e472f239672ff48860b0.tar.xz | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (37 commits)
MIPS: Only write c0_framemask on CPUs which have this register.
MIPS: Alchemy: new userspace suspend interface for development boards.
MIPS: Alchemy: dbdma suspend/resume support.
MIPS: Alchemy: Fix up PM code on Au1550/Au1200
MIPS: Alchemy: move calc_clock function.
MIPS: Alchemy: RTC counter clocksource / clockevent support.
MIPS: make cp0 counter clocksource/event usable as fallback.
MIPS: Alchemy: remove cpu_table.
MIPS: Alchemy: remove get/set_au1x00_lcd_clock().
MIPS: Print irq handler description
MIPS: Alchemy: pb1200: update CPLD cascade irq handler.
MIPS: Alchemy: update core interrupt code.
MIPS: Alchemy: move commandline mangling out of common code
MIPS: Alchemy: devboards: consolidate files
MIPS: Alchemy: Move development board code to common subdirectory
MIPS: Add Cavium OCTEON to arch/mips/Kconfig
MIPS: Add defconfig for Cavium OCTEON.
MIPS: Adjust the dma-common.c platform hooks.
MIPS: Add Cavium OCTEON slot into proper tlb category.
MIPS: Compute branch returns for Cavium OCTEON specific branch instructions.
...
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9316324..0417516 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1000,6 +1000,26 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) +/* + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. + */ +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) + +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + /* * Macros to access the floating point coprocessor control registers */ @@ -1008,6 +1028,8 @@ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\treorder\n\t" \ + /* gas fails to assemble cfc1 for some archs (octeon).*/ \ + ".set\tmips1\n\t" \ "cfc1\t%0,"STR(source)"\n\t" \ ".set\tpop" \ : "=r" (__res)); \ |