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author | David Daney <ddaney@avtrex.com> | 2008-09-23 07:05:54 (GMT) |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2008-10-11 15:18:56 (GMT) |
commit | 6aa3524c182c01b8b8b7c21c4da20c742a9b4d86 (patch) | |
tree | 245fc4e9f26ad9e7a95e83087bfcc79528d1352e /arch/mips/include/asm/processor.h | |
parent | 8192c9ea9ac44213d1266ecb64615519443979b3 (diff) | |
download | linux-fsl-qoriq-6aa3524c182c01b8b8b7c21c4da20c742a9b4d86.tar.xz |
MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
This is the main support code for the patch. Here we just add the
code, the following patches hook it up.
Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
create mode 100644 arch/mips/include/asm/watch.h
create mode 100644 arch/mips/kernel/watch.c
Diffstat (limited to 'arch/mips/include/asm/processor.h')
-rw-r--r-- | arch/mips/include/asm/processor.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index a1e4453..18ee58e 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -105,6 +105,19 @@ struct mips_dsp_state { {0,} \ } +struct mips3264_watch_reg_state { + /* The width of watchlo is 32 in a 32 bit kernel and 64 in a + 64 bit kernel. We use unsigned long as it has the same + property. */ + unsigned long watchlo[NUM_WATCH_REGS]; + /* Only the mask and IRW bits from watchhi. */ + u16 watchhi[NUM_WATCH_REGS]; +}; + +union mips_watch_reg_state { + struct mips3264_watch_reg_state mips3264; +}; + typedef struct { unsigned long seg; } mm_segment_t; @@ -137,6 +150,9 @@ struct thread_struct { /* Saved state of the DSP ASE, if available. */ struct mips_dsp_state dsp; + /* Saved watch register state, if available. */ + union mips_watch_reg_state watch; + /* Other stuff associated with the thread. */ unsigned long cp0_badvaddr; /* Last user fault */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ @@ -193,6 +209,10 @@ struct thread_struct { .dspcontrol = 0, \ }, \ /* \ + * saved watch register stuff \ + */ \ + .watch = {{{0,},},}, \ + /* \ * Other stuff associated with the process \ */ \ .cp0_badvaddr = 0, \ |