diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-10-01 19:22:39 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 18:32:34 (GMT) |
| commit | 65f1f5a2c3cdb0570806fe4e5512945673dfa199 (patch) | |
| tree | 61772813b74f1b3064a51ba37f36d6093eadeed7 /arch/mips/mm | |
| parent | 5090dfb5bcf51479370b501e934edadc4d781f67 (diff) | |
| download | linux-fsl-qoriq-65f1f5a2c3cdb0570806fe4e5512945673dfa199.tar.xz | |
Don't copy SB1 cache error handler to uncached memory.
This may have made sense on a paranoid day with pass 1 BCM1250 processors
that were throwing cache error exception left and right for no good
reason. On modern silicion that hardly makes sense and the code had
gotten just an obscurity ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-sb1.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index b215859..2f08b53 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -503,7 +503,6 @@ void sb1_cache_init(void) /* Special cache error handler for SB1 */ set_uncached_handler (0x100, &except_vec2_sb1, 0x80); - memcpy((void *)KSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80); probe_cache_sizes(); |