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author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 22:20:36 (GMT) |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 22:20:36 (GMT) |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/pci/pci-ddb5476.c | |
download | linux-fsl-qoriq-1da177e4c3f41524e886b7f1b8a0c1fc7321cac2.tar.xz |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'arch/mips/pci/pci-ddb5476.c')
-rw-r--r-- | arch/mips/pci/pci-ddb5476.c | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/arch/mips/pci/pci-ddb5476.c b/arch/mips/pci/pci-ddb5476.c new file mode 100644 index 0000000..90dd495 --- /dev/null +++ b/arch/mips/pci/pci-ddb5476.c @@ -0,0 +1,93 @@ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/pci.h> + +#include <asm/debug.h> + +#include <asm/ddb5xxx/ddb5xxx.h> + +static struct resource extpci_io_resource = { + "pci IO space", + 0x1000, /* leave some room for ISA bus */ + DDB_PCI_IO_SIZE - 1, + IORESOURCE_IO +}; + +static struct resource extpci_mem_resource = { + "pci memory space", + DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ + DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, + IORESOURCE_MEM +}; + +extern struct pci_ops ddb5476_ext_pci_ops; + +struct pci_controller ddb5476_controller = { + .pci_ops = &ddb5476_ext_pci_ops, + .io_resource = &extpci_io_resource, + .mem_resource = &extpci_mem_resource +}; + + +/* + * we fix up irqs based on the slot number. + * The first entry is at AD:11. + * + * This does not work for devices on sub-buses yet. + */ + +/* + * temporary + */ + +#define PCI_EXT_INTA 8 +#define PCI_EXT_INTB 9 +#define PCI_EXT_INTC 10 +#define PCI_EXT_INTD 11 +#define PCI_EXT_INTE 12 + +/* + * based on ddb5477 manual page 11 + */ +#define MAX_SLOT_NUM 21 +static unsigned char irq_map[MAX_SLOT_NUM] = { + [ 2] = 9, /* AD:13 USB */ + [ 3] = 10, /* AD:14 PMU */ + [ 5] = 0, /* AD:16 P2P bridge */ + [ 6] = nile4_to_irq(PCI_EXT_INTB), /* AD:17 */ + [ 7] = nile4_to_irq(PCI_EXT_INTC), /* AD:18 */ + [ 8] = nile4_to_irq(PCI_EXT_INTD), /* AD:19 */ + [ 9] = nile4_to_irq(PCI_EXT_INTA), /* AD:20 */ + [13] = 14, /* AD:24 HD controller, M5229 */ +}; + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return irq_map[slot]; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +void __init ddb_pci_reset_bus(void) +{ + u32 temp; + + /* + * I am not sure about the "official" procedure, the following + * steps work as far as I know: + * We first set PCI cold reset bit (bit 31) in PCICTRL-H. + * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. + * The same is true for both PCI channels. + */ + temp = ddb_in32(DDB_PCICTRL + 4); + temp |= 0x80000000; + ddb_out32(DDB_PCICTRL + 4, temp); + temp &= ~0xc0000000; + ddb_out32(DDB_PCICTRL + 4, temp); + +} |