diff options
| author | Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | 2008-07-16 11:21:09 (GMT) |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 09:10:35 (GMT) |
| commit | cbe9da029d9cc4fff59d559789885079a84a0af8 (patch) | |
| tree | 1730047636c75455eaf309f4e24e20de9dff54f0 /arch/sh/drivers/pci/fixups-sh7785lcr.c | |
| parent | 1eca5c92729a83f64826d15a9ecb1652dda54bcb (diff) | |
| download | linux-fsl-qoriq-cbe9da029d9cc4fff59d559789885079a84a0af8.tar.xz | |
sh: Renesas R0P7785LC0011RL board support
This adds initial support for the Renesas R0P7785LC0011RL board.
This patch supports 29bit address mode only.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/fixups-sh7785lcr.c')
| -rw-r--r-- | arch/sh/drivers/pci/fixups-sh7785lcr.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c new file mode 100644 index 0000000..4949e60 --- /dev/null +++ b/arch/sh/drivers/pci/fixups-sh7785lcr.c @@ -0,0 +1,46 @@ +/* + * arch/sh/drivers/pci/fixups-sh7785lcr.c + * + * R0P7785LC0011RL PCI fixups + * Copyright (C) 2008 Yoshihiro Shimoda + * + * Based on arch/sh/drivers/pci/fixups-r7780rp.c + * Copyright (C) 2003 Lineo uSolutions, Inc. + * Copyright (C) 2004 - 2006 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/pci.h> +#include "pci-sh4.h" + +int pci_fixup_pcic(void) +{ + pci_write_reg(0x000043ff, SH4_PCIINTM); + pci_write_reg(0x0000380f, SH4_PCIAINTM); + + pci_write_reg(0xfbb00047, SH7780_PCICMD); + pci_write_reg(0x00000000, SH7780_PCIIBAR); + + pci_write_reg(0x00011912, SH7780_PCISVID); + pci_write_reg(0x08000000, SH7780_PCICSCR0); + pci_write_reg(0x0000001b, SH7780_PCICSAR0); + pci_write_reg(0xfd000000, SH7780_PCICSCR1); + pci_write_reg(0x0000000f, SH7780_PCICSAR1); + + pci_write_reg(0xfd000000, SH7780_PCIMBR0); + pci_write_reg(0x00fc0000, SH7780_PCIMBMR0); + +#ifdef CONFIG_32BIT + pci_write_reg(0xc0000000, SH7780_PCIMBR2); + pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); +#endif + + /* Set IOBR for windows containing area specified in pci.h */ + pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)), + SH7780_PCIIOBR); + pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR); + + return 0; +} |