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| author | David S. Miller <davem@davemloft.net> | 2009-03-28 00:19:16 (GMT) |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-03-28 00:19:16 (GMT) |
| commit | a83398570e17af6bb81eb94f4f5dd356bd2828d8 (patch) | |
| tree | 5b5c7c3a56898485479291b7c964a1f3887d469c /arch/sh/mm/Kconfig | |
| parent | f9384d41c02408dd404aa64d66d0ef38adcf6479 (diff) | |
| parent | 0b4d569de222452bcb55a4a536ade6cf4d8d1e30 (diff) | |
| download | linux-fsl-qoriq-a83398570e17af6bb81eb94f4f5dd356bd2828d8.tar.xz | |
Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Diffstat (limited to 'arch/sh/mm/Kconfig')
| -rw-r--r-- | arch/sh/mm/Kconfig | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index 555ec97..10c2435 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -57,7 +57,7 @@ config 32BIT bool default y if CPU_SH5 -config PMB +config PMB_ENABLE bool "Support 32-bit physical addressing through PMB" depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) select 32BIT @@ -67,6 +67,33 @@ config PMB 32-bits through the SH-4A PMB. If this is not set, legacy 29-bit physical addressing will be used. +choice + prompt "PMB handling type" + depends on PMB_ENABLE + default PMB_FIXED + +config PMB + bool "PMB" + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) + select 32BIT + help + If you say Y here, physical addressing will be extended to + 32-bits through the SH-4A PMB. If this is not set, legacy + 29-bit physical addressing will be used. + +config PMB_FIXED + bool "fixed PMB" + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \ + CPU_SUBTYPE_SH7785) + select 32BIT + help + If this option is enabled, fixed PMB mappings are inherited + from the boot loader, and the kernel does not attempt dynamic + management. This is the closest to legacy 29-bit physical mode, + and allows systems to support up to 512MiB of system memory. + +endchoice + config X2TLB bool "Enable extended TLB mode" depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL |