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| author | Paul Mundt <lethal@linux-sh.org> | 2006-12-28 01:31:48 (GMT) |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-02-13 01:54:44 (GMT) |
| commit | 26b7a78c55fbc0e23a7dc19e89fd50f200efc002 (patch) | |
| tree | a830e70a57d4e9cbc669bc362db73ba5ace30d4d /arch/sh/mm/cache-sh4.c | |
| parent | 7a847f819063b80cc5b38d39e8aad4d60f6ca2fd (diff) | |
| download | linux-fsl-qoriq-26b7a78c55fbc0e23a7dc19e89fd50f200efc002.tar.xz | |
sh: Lazy dcache writeback optimizations.
This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.
With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.
And finally, explicitly disable the lazy writeback on SMP (SH-4A).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/cache-sh4.c')
| -rw-r--r-- | arch/sh/mm/cache-sh4.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index c695515..72bb487 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -236,10 +236,20 @@ static inline void flush_cache_4096(unsigned long start, /* * Write back & invalidate the D-cache of the page. * (To avoid "alias" issues) + * + * This uses a lazy write-back on UP, which is explicitly + * disabled on SMP. */ void flush_dcache_page(struct page *page) { - if (test_bit(PG_mapped, &page->flags)) { +#ifndef CONFIG_SMP + struct address_space *mapping = page_mapping(page); + + if (mapping && !mapping_mapped(mapping)) + set_bit(PG_dcache_dirty, &page->flags); + else +#endif + { unsigned long phys = PHYSADDR(page_address(page)); unsigned long addr = CACHE_OC_ADDRESS_ARRAY; int i, n; |