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| author | Minghuan Lian <Minghuan.Lian@freescale.com> | 2013-07-30 03:34:27 (GMT) |
|---|---|---|
| committer | Fleming Andrew-AFLEMING <AFLEMING@freescale.com> | 2013-07-30 21:26:00 (GMT) |
| commit | fa5e2936424e920f2ae217961b877aa1ac890442 (patch) | |
| tree | 04c584b7393dba7ca1153c042f69ee7ae2e33119 /arch | |
| parent | 5e2b86dced3348865dd2dc2ef50357b987269817 (diff) | |
| download | linux-fsl-qoriq-fa5e2936424e920f2ae217961b877aa1ac890442.tar.xz | |
powerpc/dts: fix sRIO and RMan error interrupts for b4860
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO and RMan EISR bit
value of error interrupts in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I3eacf5ebee6da5ac847d6ab93fe1e38a07e57176
Reviewed-on: http://git.am.freescale.net:8181/3616
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi index a166d1c..d2192e7 100644 --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi @@ -376,7 +376,7 @@ &rio { compatible = "fsl,srio"; - interrupts = <16 2 1 11>; + interrupts = <16 2 1 20>; #address-cells = <2>; #size-cells = <2>; fsl,iommu-parent = <&pamu0>; @@ -521,5 +521,6 @@ /include/ "qoriq-rman-0.dtsi" rman: rman@1e0000 { fsl,qman-channels-id = <0x820 0x821>; + interrupts = <16 2 1 20>; }; }; |