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author | Scott Wood <scottwood@freescale.com> | 2014-04-07 23:49:35 (GMT) |
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committer | Scott Wood <scottwood@freescale.com> | 2014-04-07 23:49:35 (GMT) |
commit | 62b8c978ee6b8d135d9e7953221de58000dba986 (patch) | |
tree | 683b04b2e627f6710c22c151b23c8cc9a165315e /drivers/cpufreq/exynos4210-cpufreq.c | |
parent | 78fd82238d0e5716578c326404184a27ba67fd6e (diff) | |
download | linux-fsl-qoriq-62b8c978ee6b8d135d9e7953221de58000dba986.tar.xz |
Rewind v3.13-rc3+ (78fd82238d0e5716) to v3.12
Diffstat (limited to 'drivers/cpufreq/exynos4210-cpufreq.c')
-rw-r--r-- | drivers/cpufreq/exynos4210-cpufreq.c | 68 |
1 files changed, 60 insertions, 8 deletions
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c index dfd1643..add7fbe 100644 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ b/drivers/cpufreq/exynos4210-cpufreq.c @@ -81,9 +81,9 @@ static void exynos4210_set_clkdiv(unsigned int div_index) static void exynos4210_set_apll(unsigned int index) { - unsigned int tmp, freq = apll_freq_4210[index].freq; + unsigned int tmp; - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ + /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ clk_set_parent(moutcore, mout_mpll); do { @@ -92,9 +92,21 @@ static void exynos4210_set_apll(unsigned int index) tmp &= 0x7; } while (tmp != 0x2); - clk_set_rate(mout_apll, freq * 1000); + /* 2. Set APLL Lock time */ + __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK); + + /* 3. Change PLL PMS values */ + tmp = __raw_readl(EXYNOS4_APLL_CON0); + tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); + tmp |= apll_freq_4210[index].mps; + __raw_writel(tmp, EXYNOS4_APLL_CON0); - /* MUX_CORE_SEL = APLL */ + /* 4. wait_lock_time */ + do { + tmp = __raw_readl(EXYNOS4_APLL_CON0); + } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT))); + + /* 5. MUX_CORE_SEL = APLL */ clk_set_parent(moutcore, mout_apll); do { @@ -103,15 +115,53 @@ static void exynos4210_set_apll(unsigned int index) } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } +static bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index) +{ + unsigned int old_pm = apll_freq_4210[old_index].mps >> 8; + unsigned int new_pm = apll_freq_4210[new_index].mps >> 8; + + return (old_pm == new_pm) ? 0 : 1; +} + static void exynos4210_set_frequency(unsigned int old_index, unsigned int new_index) { + unsigned int tmp; + if (old_index > new_index) { - exynos4210_set_clkdiv(new_index); - exynos4210_set_apll(new_index); + if (!exynos4210_pms_change(old_index, new_index)) { + /* 1. Change the system clock divider values */ + exynos4210_set_clkdiv(new_index); + + /* 2. Change just s value in apll m,p,s value */ + tmp = __raw_readl(EXYNOS4_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= apll_freq_4210[new_index].mps & 0x7; + __raw_writel(tmp, EXYNOS4_APLL_CON0); + } else { + /* Clock Configuration Procedure */ + /* 1. Change the system clock divider values */ + exynos4210_set_clkdiv(new_index); + /* 2. Change the apll m,p,s value */ + exynos4210_set_apll(new_index); + } } else if (old_index < new_index) { - exynos4210_set_apll(new_index); - exynos4210_set_clkdiv(new_index); + if (!exynos4210_pms_change(old_index, new_index)) { + /* 1. Change just s value in apll m,p,s value */ + tmp = __raw_readl(EXYNOS4_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= apll_freq_4210[new_index].mps & 0x7; + __raw_writel(tmp, EXYNOS4_APLL_CON0); + + /* 2. Change the system clock divider values */ + exynos4210_set_clkdiv(new_index); + } else { + /* Clock Configuration Procedure */ + /* 1. Change the apll m,p,s value */ + exynos4210_set_apll(new_index); + /* 2. Change the system clock divider values */ + exynos4210_set_clkdiv(new_index); + } } } @@ -144,6 +194,7 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) info->volt_table = exynos4210_volt_table; info->freq_table = exynos4210_freq_table; info->set_freq = exynos4210_set_frequency; + info->need_apll_change = exynos4210_pms_change; return 0; @@ -157,3 +208,4 @@ err_moutcore: pr_debug("%s: failed initialization\n", __func__); return -EINVAL; } +EXPORT_SYMBOL(exynos4210_cpufreq_init); |