diff options
| author | Vakul Garg <vakul@freescale.com> | 2013-02-08 17:14:44 (GMT) |
|---|---|---|
| committer | Emil Medve <Emilian.Medve@Freescale.com> | 2013-04-02 09:48:03 (GMT) |
| commit | 62e653aa1e47b47033604d36755971ae17a773f8 (patch) | |
| tree | d64ed08309b8139e8c103a452195c2a0470729e4 /drivers/crypto/caam/regs.h | |
| parent | 5802fdc5cbeb34a1e18cf71b8ce2258c98191198 (diff) | |
| download | linux-fsl-qoriq-62e653aa1e47b47033604d36755971ae17a773f8.tar.xz | |
crypto: caam - set RDB bit in security configuration register
This change is required for post SEC-5.0 devices which have RNG4.
Setting RDB in security configuration register allows CAAM to use the
"Random Data Buffer" to be filled by a single request. The Random Data
Buffer is large enough for ten packets to get their IVs from a single
request. If the Random Data Buffer is not enabled, then each IV causes a
separate request, and RNG4 hardware cannot keep up resulting in lower
IPSEC throughput if random IVs are used.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
(cherry picked from commit 6f06efb41aa4900d76e1ecd260b0811873f499dd)
Change-Id: I49fe9e61f70c4ad2562e1f0c0c6a1407f0f079e5
Reviewed-on: http://git.am.freescale.net:8181/525
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Diffstat (limited to 'drivers/crypto/caam/regs.h')
| -rw-r--r-- | drivers/crypto/caam/regs.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 3223fc6..cd6feda 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -252,7 +252,8 @@ struct caam_ctrl { /* Read/Writable */ u32 rsvd1; u32 mcr; /* MCFG Master Config Register */ - u32 rsvd2[2]; + u32 rsvd2; + u32 scfgr; /* SCFGR, Security Config Register */ /* Bus Access Configuration Section 010-11f */ /* Read/Writable */ @@ -299,6 +300,7 @@ struct caam_ctrl { #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ #define MCFGR_DMA_RESET 0x10000000 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ +#define SCFGR_RDBENABLE 0x00000400 /* AXI read cache control */ #define MCFGR_ARCACHE_SHIFT 12 |