crypto: caam/qi - make tls10 descriptors compatible with Era3 and Era2

Replace instructions that are not supported in Era3 and Era2.

Change-Id: I7c4c9417a66921537875b507185f60826b477c6e
Signed-off-by: Tudor Ambarus <tudor.ambarus@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10818
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Horia Ioan Geanta Neag <horia.geanta@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>

1 files changed, 32 insertions, 16 deletions

diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c
index 3dac8d1..7e85816 100644
--- a/drivers/crypto/caam/caamalg_qi.c
+++ b/drivers/crypto/caam/caamalg_qi.c
@@ -386,7 +386,7 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
 	bool keys_fit_inline = false;
 	u32 *key_jump_cmd, *zero_payload_jump_cmd, *skip_zero_jump_cmd;
-	u32 genpad, clrw, jumpback, stidx;
+	u32 genpad, jumpback, stidx;
 	u32 *desc;
 	unsigned int blocksize = crypto_aead_blocksize(aead);
 	/* Associated data length is always = 13 for TLS */
@@ -436,11 +436,11 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
 
 	/* payloadlen = input data length - (assoclen + ivlen) */
-	append_math_sub_imm_u32(desc, VARSEQINLEN, SEQINLEN, IMM, assoclen +
+	append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, assoclen +
 				tfm->ivsize);
 
 	/* math1 = payloadlen + icvlen */
-	append_math_add_imm_u32(desc, REG1, VARSEQINLEN, IMM, ctx->authsize);
+	append_math_add_imm_u32(desc, REG1, REG0, IMM, ctx->authsize);
 
 	/* padlen = block_size - math1 % block_size */
 	append_math_and_imm_u32(desc, REG3, REG1, IMM, blocksize - 1);
@@ -449,11 +449,26 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 	/* cryptlen = payloadlen + icvlen + padlen */
 	append_math_add(desc, VARSEQOUTLEN, REG1, REG2, 4);
 
+	/*
+	 * update immediate data with the padding length value
+	 * for the LOAD in the class 1 data size register.
+	 */
+	append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 |
+			(45 * 4 << MOVE_OFFSET_SHIFT) | 7);
+	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF |
+			(45 * 4 << MOVE_OFFSET_SHIFT) | 8);
+
+	/* overwrite PL field for the padding iNFO FIFO entry  */
+	append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 |
+			(47 * 4 << MOVE_OFFSET_SHIFT) | 7);
+	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF |
+			(47 * 4 << MOVE_OFFSET_SHIFT) | 8);
+
 	/* store encrypted payload, icv and padding */
 	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF);
 
 	/* if payload length is zero, jump to zero-payload commands */
-	append_math_add(desc, NONE, ZERO, VARSEQINLEN, 4);
+	append_math_add(desc, VARSEQINLEN, ZERO, REG0, 4);
 	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
 					    JUMP_COND_MATH_Z);
 
@@ -482,12 +497,15 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 	append_move(desc, MOVE_SRC_CLASS2CTX | MOVE_DEST_CLASS1INFIFO |
 		    ctx->authsize);
 
+	/* update class 1 data size register with padding length */
+	append_load_imm_u32(desc, 0, LDST_CLASS_1_CCB |
+			    LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
+
 	/* generate padding and send it to encryption */
 	genpad = NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_LC1 | NFIFOENTRY_FC1 |
 	      NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_PTYPE_N;
 	append_load_imm_u32(desc, genpad, LDST_CLASS_IND_CCB |
-			    LDST_SRCDST_WORD_INFO_FIFO_SZM | LDST_IMM |
-			    (2 & LDST_LEN_MASK));
+			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
 
 #ifdef DEBUG
 	print_hex_dump(KERN_ERR, "tls enc shdesc@"__stringify(__LINE__)": ",
@@ -546,11 +564,9 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO | MOVE_DEST_MATH0 |
 		    blocksize);
 
-	/* clear cha1 specific registers */
-	clrw = CLRW_CLR_C1MODE | CLRW_CLR_C1DATAS | CLRW_CLR_C1CTX |
-	       CLRW_RESET_CLS1_CHA;
-	append_load_imm_u32(desc, clrw, LDST_CLASS_IND_CCB |
-			    LDST_SRCDST_WORD_CLRW | LDST_IMM);
+	/* reset AES CHA */
+	append_load_imm_u32(desc, CCTRL_RESET_CHA_AESA, LDST_CLASS_IND_CCB |
+			    LDST_SRCDST_WORD_CHACTRL | LDST_IMM);
 
 	/* rewind input sequence */
 	append_seq_in_ptr_intlen(desc, 0, 65535, SQIN_RTO);
@@ -563,7 +579,7 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG);
 	/* load Type, Version and Len fields in math0 */
 	append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_DECO |
-		   LDST_SRCDST_WORD_DECO_MATH0 | 5);
+		   LDST_SRCDST_WORD_DECO_MATH0 | (3 << LDST_OFFSET_SHIFT) | 5);
 
 	/* load iv in context1 */
 	append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_1_CCB |
@@ -581,7 +597,6 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, 4);
 
 	/* update Len field */
-	append_math_rshift_imm_u64(desc, REG0, REG0, IMM, 24);
 	append_math_sub(desc, REG0, REG0, REG2, 8);
 
 	/* store decrypted payload, icv and padding */
@@ -622,7 +637,7 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 
 	/* move seqoutptr fields into math registers */
 	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | MOVE_DEST_MATH0 |
-			(55 * 4 << MOVE_OFFSET_SHIFT) | 20);
+			(54 * 4 << MOVE_OFFSET_SHIFT) | 20);
 	/* seqinptr will point to seqoutptr */
 	append_math_and_imm_u32(desc, REG0, REG0, IMM,
 				~(CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR));
@@ -631,9 +646,10 @@ static int tls_set_sh_desc(struct crypto_aead *aead)
 	append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM |
 			    LDST_SRCDST_WORD_DECO_MATH2 |
 			    (4 << LDST_OFFSET_SHIFT));
+	append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1);
 	/* move updated seqinptr fields to JD */
 	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | MOVE_DEST_DESCBUF |
-			(55 * 4 << MOVE_OFFSET_SHIFT) | 24);
+			(54 * 4 << MOVE_OFFSET_SHIFT) | 24);
 	/* read updated seqinptr */
 	append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 6);
 
@@ -2040,7 +2056,7 @@ static struct caam_alg_template driver_algs[] = {
 		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
 		.class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
 		.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
-		.min_era = 4,
+		.min_era = 2,
 	}
 };