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authorSteve Wise <swise@opengridcomputing.com>2010-09-10 16:14:53 (GMT)
committerRoland Dreier <rolandd@cisco.com>2010-09-28 17:46:30 (GMT)
commit13fecb83b410b147343e6c7b0427d244ef77b526 (patch)
tree452a4df2f7703f74872d72a982fa703b03582280 /drivers/infiniband/hw/cxgb4
parentaf93fb5dcc6b1cba5fd0861d349b3f9c93144bc0 (diff)
downloadlinux-fsl-qoriq-13fecb83b410b147343e6c7b0427d244ef77b526.tar.xz
RDMA/cxgb4: Zero out ISGL padding
The HW design requires zeroing any pad in SGLs. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb4')
-rw-r--r--drivers/infiniband/hw/cxgb4/qp.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index 4f5dd66..bdbf54d 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -263,6 +263,9 @@ static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
rem -= len;
}
}
+ len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
+ if (len)
+ memset(dstp, 0, len);
immdp->op = FW_RI_DATA_IMMD;
immdp->r1 = 0;
immdp->r2 = 0;
@@ -292,6 +295,7 @@ static int build_isgl(__be64 *queue_start, __be64 *queue_end,
if (++flitp == queue_end)
flitp = queue_start;
}
+ *flitp = (__force __be64)0;
isglp->op = FW_RI_DATA_ISGL;
isglp->r1 = 0;
isglp->nsge = cpu_to_be16(num_sge);