diff options
| author | Stephen Warren <swarren@nvidia.com> | 2013-03-05 00:10:20 (GMT) |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2013-03-05 02:42:11 (GMT) |
| commit | 0af18c5cc9403999bb189f825b816f7fc80fc0ee (patch) | |
| tree | ec65734228968d4948dd50b9551aaea799058558 /sound/soc/tegra/tegra20_i2s.h | |
| parent | 6dbe51c251a327e012439c4772097a13df43c5b8 (diff) | |
| download | linux-fsl-qoriq-0af18c5cc9403999bb189f825b816f7fc80fc0ee.tar.xz | |
ASoC: tegra: fix I2S bit count mask
This register field is 11 bits wide, not 15 bits wide. Given the way
this value is currently, used, this patch has no practical effect.
However, it's still best if the value is correct.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/tegra/tegra20_i2s.h')
| -rw-r--r-- | sound/soc/tegra/tegra20_i2s.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/tegra/tegra20_i2s.h b/sound/soc/tegra/tegra20_i2s.h index c27069d..7299587 100644 --- a/sound/soc/tegra/tegra20_i2s.h +++ b/sound/soc/tegra/tegra20_i2s.h @@ -121,7 +121,7 @@ #define TEGRA20_I2S_TIMING_NON_SYM_ENABLE (1 << 12) #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0 -#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7fff +#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT) /* Fields in TEGRA20_I2S_FIFO_SCR */ |