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| author | Alex Deucher <alexander.deucher@amd.com> | 2012-04-20 16:39:49 (GMT) |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-26 20:11:47 (GMT) |
| commit | 1d5d0c349790b66fcd338f0b5ce04b9aa7483118 (patch) | |
| tree | 05226a461ae1f6049164d9d4dbc5280b339ad7f7 | |
| parent | cc066715e6e164032ab382625cd311079a2f90ac (diff) | |
| download | linux-fsl-qoriq-1d5d0c349790b66fcd338f0b5ce04b9aa7483118.tar.xz | |
drm/radeon: add indirect register accessors for SMC registers
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen_reg.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 17 |
2 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h index 881aba2..50948ac 100644 --- a/drivers/gpu/drm/radeon/evergreen_reg.h +++ b/drivers/gpu/drm/radeon/evergreen_reg.h @@ -24,6 +24,10 @@ #ifndef __EVERGREEN_REG_H__ #define __EVERGREEN_REG_H__ +/* trinity */ +#define TN_SMC_IND_INDEX_0 0x200 +#define TN_SMC_IND_DATA_0 0x204 + /* evergreen */ #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index b329e99..9af0fa6 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1806,6 +1806,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) +#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) +#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ @@ -1844,6 +1846,21 @@ static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uin WREG32(RADEON_PCIE_DATA, (v)); } +static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) +{ + u32 r; + + WREG32(TN_SMC_IND_INDEX_0, (reg)); + r = RREG32(TN_SMC_IND_DATA_0); + return r; +} + +static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + WREG32(TN_SMC_IND_INDEX_0, (reg)); + WREG32(TN_SMC_IND_DATA_0, (v)); +} + void r100_pll_errata_after_index(struct radeon_device *rdev); |