powerpc/mpc85xx: Update the clockgen node in dts

According to the e500mc hardware specification, the e500mc core
can run at e500mc core complex PLL/1, PLL/2.
So, for safety sake, we remove the PLL/4 on the platforms
p2041rdb, p3041ds and p5020ds which can take PLL/4 as input clock.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I9e8f68a8c8f8714e4c17a055949943ad8261f8f6
Reviewed-on: http://git.am.freescale.net:8181/2503
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>

3 files changed, 26 insertions, 46 deletions

diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 42b282f3..204a9ad 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -327,53 +327,45 @@
 			reg = <0x800>;
 			compatible = "fsl,core-pll-clock";
 			clocks = <&clockgen>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+			clock-output-names = "pll0", "pll0-div2";
 		};
 		pll1: pll1@820 {
 			#clock-cells = <1>;
 			reg = <0x820>;
 			compatible = "fsl,core-pll-clock";
 			clocks = <&clockgen>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+			clock-output-names = "pll1", "pll1-div2";
 		};
 		mux0: mux0@0 {
 			#clock-cells = <0>;
 			reg = <0x0>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				   <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux0";
 		};
 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				   <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux1";
 		};
 		mux2: mux2@40 {
 			#clock-cells = <0>;
 			reg = <0x40>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				   <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux2";
 		};
 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				   <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux3";
 		};
 	};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 5ee9731..3191d54 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -354,53 +354,45 @@
 			reg = <0x800>;
 			compatible = "fsl,core-pll-clock";
 			clocks = <&clockgen>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+			clock-output-names = "pll0", "pll0-div2";
 		};
 		pll1: pll1@820 {
 			#clock-cells = <1>;
 			reg = <0x820>;
 			compatible = "fsl,core-pll-clock";
 			clocks = <&clockgen>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+			clock-output-names = "pll1", "pll1-div2";
 		};
 		mux0: mux0@0 {
 			#clock-cells = <0>;
 			reg = <0x0>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux0";
 		};
 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux1";
 		};
 		mux2: mux2@40 {
 			#clock-cells = <0>;
 			reg = <0x40>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux2";
 		};
 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux3";
 		};
 	};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 23ee8f0..0c3ae85 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -359,33 +359,29 @@
 			reg = <0x800>;
 			compatible = "fsl,core-pll-clock";
 			clocks = <&clockgen>;
-			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+			clock-output-names = "pll0", "pll0-div2";
 		};
 		pll1: pll1@820 {
 			#clock-cells = <1>;
 			reg = <0x820>;
 			compatible = "fsl,core-pll-clock";
 			clocks = <&clockgen>;
-			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+			clock-output-names = "pll1", "pll1-div2";
 		};
 		mux0: mux0@0 {
 			#clock-cells = <0>;
 			reg = <0x0>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux0";
 		};
 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20>;
 			compatible = "fsl,core-mux-clock";
-			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
-				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
-			clock-names = "pll0_0", "pll0_1", "pll0_2",
-				"pll1_0", "pll1_1", "pll1_2";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
 			clock-output-names = "cmux1";
 		};
 	};