diff options
| author | Roland Stigge <stigge@antcom.de> | 2012-02-27 16:28:02 (GMT) |
|---|---|---|
| committer | Roland Stigge <stigge@antcom.de> | 2012-02-27 16:28:02 (GMT) |
| commit | 35dd0a75d4a382e7f769dd0277732e7aa5235718 (patch) | |
| tree | 1551ad6bdb769fc20871e9c8497fcc8fe068c160 | |
| parent | f6737055c1c432a9628a9a731f9881ad8e0a9eee (diff) | |
| download | linux-fsl-qoriq-35dd0a75d4a382e7f769dd0277732e7aa5235718.tar.xz | |
ARM: LPC32xx: Fix interrupt controller init
This patch fixes the initialization of the interrupt controller of the LPC32xx
by correctly setting up SIC1 and SIC2 instead of (wrongly) using the same value
as for the Main Interrupt Controller (MIC).
Signed-off-by: Roland Stigge <stigge@antcom.de>
Cc: stable@vger.kernel.org
| -rw-r--r-- | arch/arm/mach-lpc32xx/irq.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index ce4b557..d3bf9c1 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -384,13 +384,15 @@ void __init lpc32xx_init_irq(void) /* Setup SIC1 */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); + __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); + __raw_writel(SIC1_ATR_DEFAULT, + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); /* Setup SIC2 */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); + __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); + __raw_writel(SIC2_ATR_DEFAULT, + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); /* Configure supported IRQ's */ for (i = 0; i < NR_IRQS; i++) { |