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| author | Xie Xiaobo <X.Xie@freescale.com> | 2013-11-14 06:59:57 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-05-21 13:28:55 (GMT) |
| commit | 589b6bc9b283455d83290d6986cac9914f1c4d5f (patch) | |
| tree | 9428d5e47f47fa6851a12d7b4adcdefbb0596097 | |
| parent | ab37c39b6333cb6d20dfa1d2f97be826474294ed (diff) | |
| download | linux-fsl-qoriq-589b6bc9b283455d83290d6986cac9914f1c4d5f.tar.xz | |
powerpc/85xx: p1025twr: add module conditional to fix QE-uart issue
A ioport setting was needed when used the QE uart function on TWR-P1025.
Added a conditional definition to avoid missing this setting when the
QE-uart driver was bulit to a module.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Change-Id: I95b40c760335ce5fa7a27a94287dbef28219b5fa
Reviewed-on: http://git.am.freescale.net:8181/6643
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/12045
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
| -rw-r--r-- | arch/powerpc/platforms/85xx/twr_p102x.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 383eb57..4e119ac 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -139,7 +139,7 @@ static void __init twr_p1025_setup_arch(void) MPC85xx_PMUXCR_QE(12)); iounmap(guts); -#if defined(CONFIG_SERIAL_QE) +#if defined(CONFIG_SERIAL_QE) || defined(CONFIG_SERIAL_QE_MODULE) /* On P1025TWR board, the UCC7 acted as UART port. * However, The UCC7's CTS pin is low level in default, * it will impact the transmission in full duplex |