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| author | Alex Deucher <alexander.deucher@amd.com> | 2012-07-13 15:04:37 (GMT) |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-26 20:11:41 (GMT) |
| commit | 8542c12b4c960c7ce0a4cf1d7e34b9815e9fe8cc (patch) | |
| tree | 26817a1d019831a53fc0b281f78a709e47865847 | |
| parent | aea6564133f07dde1c47dbde2f7c198a2e8361d5 (diff) | |
| download | linux-fsl-qoriq-8542c12b4c960c7ce0a4cf1d7e34b9815e9fe8cc.tar.xz | |
drm/radeon: update DISPCLK programming for DCE8
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 4ba5184..586c452 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -743,7 +743,7 @@ static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, * SetPixelClock provides the dividers */ args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); - if (ASIC_IS_DCE61(rdev)) + if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) args.v6.ucPpll = ATOM_EXT_PLL1; else if (ASIC_IS_DCE6(rdev)) args.v6.ucPpll = ATOM_PPLL0; |