powerpc/85xx: Enhance cache-sram kernel boot parameter

Two command line parameters are combined into one since they
should always be used simultaneously.
The term offset is misleading, replace it with addr as it
represents a physical address.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I46cb777524248c3cc9c84b6e131a5cb513a652ab
Reviewed-on: http://git.am.freescale.net:8181/1237
Reviewed-by: Tang Yuantian-B29983 <yuantian.tang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>

5 files changed, 26 insertions, 25 deletions

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 1ba0afe..f113ce3 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -439,6 +439,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 
 	c101=		[NET] Moxa C101 synchronous serial card
 
+	cache-sram=     [HW] Create a cache-based SRAM.
+			Format: <phys-addr>,<size>
+
 	cachesize=	[BUGS=X86-32] Override level 2 CPU cache size detection.
 			Sometimes CPU hardware bugs make them report the cache
 			size incorrectly. The kernel will attempt work arounds
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 5368ca4..c58ee7b 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -21,8 +21,8 @@ config FSL_85XX_CACHE_SRAM
 	help
 	  When selected, this option enables cache-sram support
 	  for memory allocation on P1/P2 QorIQ platforms.
-	  cache-sram-size and cache-sram-offset kernel boot
-	  parameters should be passed when this option is enabled.
+	  cache-sram kernel boot parameters should be passed when
+	  this option is enabled.
 
 config BSC9131_RDB
 	bool "Freescale BSC9131RDB"
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
index 2aa97ddb..b8096a1 100644
--- a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -91,7 +91,7 @@ struct mpc85xx_l2ctlr {
 
 struct sram_parameters {
 	unsigned int sram_size;
-	phys_addr_t sram_offset;
+	phys_addr_t sram_addr;
 };
 
 extern int instantiate_cache_sram(struct platform_device *dev,
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
index 37a6909..25111e0 100644
--- a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
@@ -96,7 +96,7 @@ int __init instantiate_cache_sram(struct platform_device *dev,
 		return -ENOMEM;
 	}
 
-	cache_sram->base_phys = sram_params.sram_offset;
+	cache_sram->base_phys = sram_params.sram_addr;
 	cache_sram->size = sram_params.sram_size;
 
 	if (!request_mem_region(cache_sram->base_phys, cache_sram->size,
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index afc2dbf..5eedf74 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -27,47 +27,45 @@
 
 #include "fsl_85xx_cache_ctlr.h"
 
-static char *sram_size;
-static char *sram_offset;
+static char *cache_sram;
 struct mpc85xx_l2ctlr __iomem *l2ctlr;
 
 static int get_cache_sram_params(struct sram_parameters *sram_params)
 {
 	unsigned long long addr;
 	unsigned int size;
+	char *str;
 
-	if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))
+	if (!cache_sram)
 		return -EINVAL;
 
-	if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))
+	str = strchr(cache_sram, ',');
+	if (!str)
 		return -EINVAL;
 
-	sram_params->sram_offset = addr;
-	sram_params->sram_size = size;
+	*str = 0;
+	str++;
 
-	return 0;
-}
+	if (kstrtouint(str, 0, &size) < 0 ||
+			kstrtoull(cache_sram, 0, &addr) < 0)
+		return -EINVAL;
 
-static int __init get_size_from_cmdline(char *str)
-{
-	if (!str)
-		return 0;
+	sram_params->sram_addr = addr;
+	sram_params->sram_size = size;
 
-	sram_size = str;
-	return 1;
+	return 0;
 }
 
-static int __init get_offset_from_cmdline(char *str)
+static int __init get_cache_sram_cmdline(char *str)
 {
 	if (!str)
 		return 0;
 
-	sram_offset = str;
+	cache_sram = str;
 	return 1;
 }
 
-__setup("cache-sram-size=", get_size_from_cmdline);
-__setup("cache-sram-offset=", get_offset_from_cmdline);
+__setup("cache-sram=", get_cache_sram_cmdline);
 
 static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
 {
@@ -92,7 +90,7 @@ static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
 
 	if (get_cache_sram_params(&sram_params)) {
 		dev_err(&dev->dev,
-			"Entire L2 as cache, provide valid sram offset and size\n");
+			"Entire L2 as cache, provide valid sram address and size\n");
 		return -EINVAL;
 	}
 
@@ -114,14 +112,14 @@ static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
 	 * Write bits[0-17] to srbar0
 	 */
 	out_be32(&l2ctlr->srbar0,
-		lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);
+		lower_32_bits(sram_params.sram_addr) & L2SRAM_BAR_MSK_LO18);
 
 	/*
 	 * Write bits[18-21] to srbare0
 	 */
 #ifdef CONFIG_PHYS_64BIT
 	out_be32(&l2ctlr->srbarea0,
-		upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);
+		upper_32_bits(sram_params.sram_addr) & L2SRAM_BARE_MSK_HI4);
 #endif
 
 	clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);