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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-10-02 08:33:36 (GMT)
committerSimon Horman <horms+renesas@verge.net.au>2013-10-08 01:02:22 (GMT)
commit90357fcbf2fcb9e50899fd3b2a91a6dc3cfe5ea5 (patch)
treed44ed89d215fec3de58ce14df3c307e2e42c0111
parentb6d5a1b1c3476225e897a2f706c0e7eca7b05984 (diff)
downloadlinux-fsl-qoriq-90357fcbf2fcb9e50899fd3b2a91a6dc3cfe5ea5.tar.xz
ARM: shmobile: bockw: add SMSC support on reference
This patch enables INTC IRQ, and SMSC IRQ. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/mach-shmobile/board-bockw-reference.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index 1a7c893..ae88fda 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -36,15 +36,35 @@ static const struct pinctrl_map bockw_pinctrl_map[] = {
"scif0_ctrl", "scif0"),
};
+#define FPGA 0x18200000
+#define IRQ0MR 0x30
+#define COMCTLR 0x101c
static void __init bockw_init(void)
{
+ static void __iomem *fpga;
+
r8a7778_clock_init();
+ r8a7778_init_irq_extpin_dt(1);
pinctrl_register_mappings(bockw_pinctrl_map,
ARRAY_SIZE(bockw_pinctrl_map));
r8a7778_pinmux_init();
r8a7778_add_dt_devices();
+ fpga = ioremap_nocache(FPGA, SZ_1M);
+ if (fpga) {
+ /*
+ * CAUTION
+ *
+ * IRQ0/1 is cascaded interrupt from FPGA.
+ * it should be cared in the future
+ * Now, it is assuming IRQ0 was used only from SMSC.
+ */
+ u16 val = ioread16(fpga + IRQ0MR);
+ val &= ~(1 << 4); /* enable SMSC911x */
+ iowrite16(val, fpga + IRQ0MR);
+ }
+
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}