diff options
| author | Tony Prisk <linux@prisktech.co.nz> | 2013-05-10 05:44:58 (GMT) |
|---|---|---|
| committer | Tony Prisk <linux@prisktech.co.nz> | 2013-05-12 08:31:15 (GMT) |
| commit | 9e7b6d3eda8551912b0cf9507ca5f489a476d522 (patch) | |
| tree | 668e16d24fbdde20ce575218bd2a175f7bf4e182 | |
| parent | 5c2b0a8531f594db82abc29e786b4c2d38fa298b (diff) | |
| download | linux-fsl-qoriq-9e7b6d3eda8551912b0cf9507ca5f489a476d522.tar.xz | |
dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files
Add support for the ARM, AHB, APB and DDR clocks found on the
WM8505, WM8650, WM8750 and WM8850 SoCs.
These clocks are gateable, but the enable part of the clock definition
is left out as there are no users for these clocks, and we don't want
them being disabled at boot, but it does provide users the ability to
check the current rate of these clocks.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
| -rw-r--r-- | arch/arm/boot/dts/wm8505.dtsi | 28 | ||||
| -rw-r--r-- | arch/arm/boot/dts/wm8650.dtsi | 37 | ||||
| -rw-r--r-- | arch/arm/boot/dts/wm8750.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/wm8850.dtsi | 28 |
4 files changed, 92 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 702d866..a1a854b 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -109,6 +109,34 @@ reg = <0x20c>; }; + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index 46a4603..7525982 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -113,6 +113,34 @@ reg = <0x210>; }; + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; @@ -129,14 +157,7 @@ enable-bit = <2>; }; - arm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - sdhc: sdhc { + clksdhc: sdhc { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; clocks = <&pllb>; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi index e4a1e85..557a9c2a 100644 --- a/arch/arm/boot/dts/wm8750.dtsi +++ b/arch/arm/boot/dts/wm8750.dtsi @@ -133,6 +133,13 @@ divisor-reg = <0x304>; }; + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + clkddr: ddr { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index 59aaad9..1f49f54 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -130,6 +130,34 @@ reg = <0x218>; }; + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; |