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| author | Ben Skeggs <bskeggs@redhat.com> | 2013-01-31 22:43:55 (GMT) |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-02-20 06:00:47 (GMT) |
| commit | a2fa297378c54e9b8b8ad355e34c9fbed730250b (patch) | |
| tree | 77b462f24cc8978fa95333def69ab192063d1c17 | |
| parent | 750087f1245e5a5d0692de4e3e7dd76d0f5b5b0a (diff) | |
| download | linux-fsl-qoriq-a2fa297378c54e9b8b8ad355e34c9fbed730250b.tar.xz | |
drm/nouveau/fifo/nvc0: bash some magic reg to make uevent interrupt work
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index bf86f40..4f226af 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c @@ -706,6 +706,7 @@ nvc0_fifo_init(struct nouveau_object *object) nv_wr32(priv, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */ nv_wr32(priv, 0x002100, 0xffffffff); nv_wr32(priv, 0x002140, 0x3fffffff); + nv_wr32(priv, 0x002628, 0x00000001); /* makes mthd 0x20 work */ return 0; } |