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author | Tom Huynh <tom.huynh@freescale.com> | 2015-01-22 22:29:36 (GMT) |
---|---|---|
committer | Honghua Yin <Hong-Hua.Yin@freescale.com> | 2015-03-16 08:28:49 (GMT) |
commit | a82bc85b91aabe41b47eb7ef4b15c466f671ecbc (patch) | |
tree | f59b8596d188480dfba921dc598a4cbebd06fd94 | |
parent | 64ded519fc23ff43dc257dce37dfd1b7801f1e99 (diff) | |
download | linux-fsl-qoriq-a82bc85b91aabe41b47eb7ef4b15c466f671ecbc.tar.xz |
powerpc/perf: fix fsl_emb_pmu_start to write correct pmc value
PMCs on PowerPC increases towards 0x80000000 and triggers an overflow
interrupt when the msb is set to collect a sample. Therefore, to setup
for the next sample collection, pmu_start should set the pmc value to
0x80000000 - left instead of left which incorrectly delays the next
overflow interrupt. Same as commit 9a45a9407c69 ("powerpc/perf:
power_pmu_start restores incorrect values, breaking frequency events")
for book3s.
Change-Id: I5ba1acaec8436973970d00fdbd4b100107559a32
Reviewed-on: http://git.am.freescale.net:8181/29119
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
-rw-r--r-- | arch/powerpc/perf/core-fsl-emb.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c index d35ae52..6e92050 100644 --- a/arch/powerpc/perf/core-fsl-emb.c +++ b/arch/powerpc/perf/core-fsl-emb.c @@ -389,6 +389,7 @@ static void fsl_emb_pmu_del(struct perf_event *event, int flags) static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags) { unsigned long flags; + unsigned long val; s64 left; if (event->hw.idx < 0 || !event->hw.sample_period) @@ -405,7 +406,10 @@ static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags) event->hw.state = 0; left = local64_read(&event->hw.period_left); - write_pmc(event->hw.idx, left); + val = 0; + if (left < 0x80000000L) + val = 0x80000000L - left; + write_pmc(event->hw.idx, val); perf_event_update_userpage(event); perf_pmu_enable(event->pmu); |