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| author | Ben Skeggs <bskeggs@redhat.com> | 2013-10-11 04:42:47 (GMT) |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-11-08 05:39:05 (GMT) |
| commit | ab5beca895335856ed9cb749aee8a2aabde0c247 (patch) | |
| tree | 90a5ca73eb476487b80324693317dffbd28dea4a | |
| parent | 6dcee40a9bc5fefea324581bea3a39be153c2572 (diff) | |
| download | linux-fsl-qoriq-ab5beca895335856ed9cb749aee8a2aabde0c247.tar.xz | |
drm/nouveau/mc: bracket interrupt handler with NV_PMC_INTR_EN disable/re-enable
This looks to be what NVIDIA do pretty much everywhere, since forever.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/mc/base.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c index f26fcbd..b643722 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c @@ -33,6 +33,9 @@ nouveau_mc_intr(int irq, void *arg) struct nouveau_subdev *unit; u32 intr, stat; + nv_wr32(pmc, 0x000140, 0x00000000); + nv_rd32(pmc, 0x000140); + intr = nv_rd32(pmc, 0x000100); if (intr == 0xffffffff) /* likely fallen off the bus */ intr = 0x00000000; @@ -54,6 +57,7 @@ nouveau_mc_intr(int irq, void *arg) nv_error(pmc, "unknown intr 0x%08x\n", stat); } + nv_wr32(pmc, 0x000140, 0x00000001); return intr ? IRQ_HANDLED : IRQ_NONE; } |