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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-31 20:12:38 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-11 22:51:18 (GMT) |
| commit | b6b4e185a7d2835fa145bf1a2e3553431cb24a92 (patch) | |
| tree | 8e3b926d38d3530360c723f0fc6d00bf29b377bf | |
| parent | 8c52b5e8554d21b1cb69836f04c9dbe483915b86 (diff) | |
| download | linux-fsl-qoriq-b6b4e185a7d2835fa145bf1a2e3553431cb24a92.tar.xz | |
drm/i915: rename intel_enable_pch_pll to ironlake_enable_pch_pll
Because this function is only for the older PCHs, not the newer ones.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 28b9d66..22da6d1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1579,14 +1579,14 @@ out_unlock: } /** - * intel_enable_pch_pll - enable PCH PLL + * ironlake_enable_pch_pll - enable PCH PLL * @dev_priv: i915 private structure * @pipe: pipe PLL to enable * * The PCH PLL needs to be enabled before the PCH transcoder, since it * drives the transcoder clock. */ -static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) +static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) { struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; struct intel_pch_pll *pll; @@ -3084,7 +3084,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) * Note that enable_pch_pll tries to do the right thing, but get_pch_pll * unconditionally resets the pll - we need that to have the right LVDS * enable sequence. */ - intel_enable_pch_pll(intel_crtc); + ironlake_enable_pch_pll(intel_crtc); if (HAS_PCH_CPT(dev)) { u32 sel; @@ -3188,7 +3188,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc) * Note that enable_pch_pll tries to do the right thing, but get_pch_pll * unconditionally resets the pll - we need that to have the right LVDS * enable sequence. */ - intel_enable_pch_pll(intel_crtc); + ironlake_enable_pch_pll(intel_crtc); lpt_program_iclkip(crtc); |