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author | Wang Dongsheng <dongsheng.wang@freescale.com> | 2013-05-16 10:27:26 (GMT) |
---|---|---|
committer | Fleming Andrew-AFLEMING <AFLEMING@freescale.com> | 2013-05-17 00:53:10 (GMT) |
commit | b81dba7e73ffb253a41b6a85e9bff9a1a2dc1d12 (patch) | |
tree | 46c6f86de7de1cd4c7a519bc99bc822d5a61074c | |
parent | 8e2b904efa843199b2cd29919d835a3e231b14b3 (diff) | |
download | linux-fsl-qoriq-b81dba7e73ffb253a41b6a85e9bff9a1a2dc1d12.tar.xz |
powerpc/dts: fix lbc lack of error interrupt
P1020, P1021, P1022, P1023 when the lbc get error, the error
interrupt will be triggered. The corresponding interrupt is
internal IRQ0. So system have to process the lbc IRQ0 interrupt.
The corresponding lbc general interrupt is internal IRQ3
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Ice300265ca9e6bec361b8804ebe97677bbbc5db8
Reviewed-on: http://git.am.freescale.net:8181/2468
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
-rw-r--r-- | arch/powerpc/boot/dts/fsl/p1020si-post.dtsi | 3 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 3 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/fsl/p1022si-post.dtsi | 3 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/fsl/p1023si-post.dtsi | 3 |
4 files changed, 8 insertions, 4 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi index 5cc07a5..1251ee1 100644 --- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi @@ -36,7 +36,8 @@ #address-cells = <2>; #size-cells = <1>; compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; - interrupts = <19 2 0 0>; + interrupts = <19 2 0 0 + 16 2 0 0>; }; /* controller at 0x9000 */ diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi index 39e8a45..06522fa 100644 --- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi @@ -36,7 +36,8 @@ #address-cells = <2>; #size-cells = <1>; compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus"; - interrupts = <19 2 0 0>; + interrupts = <19 2 0 0 + 16 2 0 0>; }; /* controller at 0x9000 */ diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi index c6fff1d..1f189a9 100644 --- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi @@ -40,7 +40,8 @@ * pin muxing when the DIU is enabled. */ compatible = "fsl,p1022-elbc", "fsl,elbc"; - interrupts = <19 2 0 0>; + interrupts = <19 2 0 0 + 16 2 0 0>; }; /* controller at 0x9000 */ diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi index bb32dbd..95c4ac0 100644 --- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi @@ -36,7 +36,8 @@ #address-cells = <2>; #size-cells = <1>; compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus"; - interrupts = <19 2 0 0>; + interrupts = <19 2 0 0 + 16 2 0 0>; }; /* controller at 0xa000 */ |