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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-08-06 08:33:03 (GMT) |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2013-08-23 18:38:07 (GMT) |
| commit | b84a76ae73b915124a5466035f187ab20a49fb6e (patch) | |
| tree | 87df9d3649b8d707f559a2ebb47c9f54e7baf139 | |
| parent | 1721c70235f59ce75bfb34d7fa9fc11143ecdb78 (diff) | |
| download | linux-fsl-qoriq-b84a76ae73b915124a5466035f187ab20a49fb6e.tar.xz | |
ARM: OMAP: AM33xx: clock: Add RNG clock data
Add clock data for RNG module on AM33xx SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
| -rw-r--r-- | arch/arm/mach-omap2/cclock33xx_data.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index ba6534d..865d30e 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -421,6 +421,10 @@ static struct clk aes0_fck; DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); +static struct clk rng_fck; +DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL); +DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null); + /* * Modules clock nodes * @@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), CLK(NULL, "sha0_fck", &sha0_fck), CLK(NULL, "aes0_fck", &aes0_fck), + CLK(NULL, "rng_fck", &rng_fck), CLK(NULL, "timer1_fck", &timer1_fck), CLK(NULL, "timer2_fck", &timer2_fck), CLK(NULL, "timer3_fck", &timer3_fck), |