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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-11 07:32:21 (GMT) |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-11 07:32:21 (GMT) |
commit | 05ad391dbc2bd27b8d868cf9c3ec1b68a2126a16 (patch) | |
tree | abfc59028a00a15428ab8b14abe8a9e99f69a9a3 /Documentation/arm64 | |
parent | 8b5baa460b69c27389353eeff0dbe51dc695da60 (diff) | |
parent | 67317c2689567c24d18e0dd43ab6d409fd42dc6e (diff) | |
download | linux-fsl-qoriq-05ad391dbc2bd27b8d868cf9c3ec1b68a2126a16.tar.xz |
Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64
Pull ARM64 update from Catalin Marinas:
"Main features:
- Ticket-based spinlock implementation and lockless lockref support
- Big endian support
- CPU hotplug support, currently for PSCI (Power State Coordination
Interface) capable firmware
- Virtual address space extended to 42-bit in the 64K page
configuration (maximum VA space with 2 levels of page tables)
- Compat (AArch32) kuser helpers updated to ARMv8 (make use of
load-acquire/store-release instructions)
- Code cleanup, defconfig update and minor fixes"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (43 commits)
ARM64: /proc/interrupts: display IPIs of online CPUs only
arm64: locks: Remove CONFIG_GENERIC_LOCKBREAK
arm64: KVM: vgic: byteswap GICv2 access on world switch if BE
arm64: KVM: initialize HYP mode following the kernel endianness
arm64: compat: Clear the IT state independent of the 32-bit ARM or Thumb-2 mode
arm64: Use 42-bit address space with 64K pages
arm64: module: ensure instruction is little-endian before manipulation
arm64: defconfig: Enable CONFIG_PREEMPT by default
arm64: fix access to preempt_count from assembly code
arm64: move enabling of GIC before CPUs are set online
arm64: use generic RW_DATA_SECTION macro in linker script
arm64: Slightly improve the warning on CPU0 enable-method
ARM64: simplify cpu_read_bootcpu_ops using OF/DT helper
ARM64: DT: define ARM64 specific arch_match_cpu_phys_id
arm64: allow ioremap_cache() to use existing RAM mappings
arm64: update 32-bit kuser helpers to ARMv8
arm64: perf: fix event number mask
arm64: kconfig: allow CPU_BIG_ENDIAN to be selected
arm64: Fix the endianness of arch_spinlock_t
arm64: big-endian: write CPU holding pen address as LE
...
Diffstat (limited to 'Documentation/arm64')
-rw-r--r-- | Documentation/arm64/booting.txt | 45 | ||||
-rw-r--r-- | Documentation/arm64/memory.txt | 29 |
2 files changed, 58 insertions, 16 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 98df4a0..a9691cc 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -115,9 +115,10 @@ Before jumping into the kernel, the following conditions must be met: External caches (if present) must be configured and disabled. - Architected timers - CNTFRQ must be programmed with the timer frequency. - If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) - set where available. + CNTFRQ must be programmed with the timer frequency and CNTVOFF must + be programmed with a consistent value on all CPUs. If entering the + kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where + available. - Coherency All CPUs to be booted by the kernel must be part of the same coherency @@ -130,30 +131,46 @@ Before jumping into the kernel, the following conditions must be met: the kernel image will be entered must be initialised by software at a higher exception level to prevent execution in an UNKNOWN state. +The requirements described above for CPU mode, caches, MMUs, architected +timers, coherency and system registers apply to all CPUs. All CPUs must +enter the kernel in the same exception level. + The boot loader is expected to enter the kernel on each CPU in the following manner: - The primary CPU must jump directly to the first instruction of the kernel image. The device tree blob passed by this CPU must contain - for each CPU node: - - 1. An 'enable-method' property. Currently, the only supported value - for this field is the string "spin-table". - - 2. A 'cpu-release-addr' property identifying a 64-bit, - zero-initialised memory location. + an 'enable-method' property for each cpu node. The supported + enable-methods are described below. It is expected that the bootloader will generate these device tree properties and insert them into the blob prior to kernel entry. -- Any secondary CPUs must spin outside of the kernel in a reserved area - of memory (communicated to the kernel by a /memreserve/ region in the +- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr' + property in their cpu node. This property identifies a + naturally-aligned 64-bit zero-initalised memory location. + + These CPUs should spin outside of the kernel in a reserved area of + memory (communicated to the kernel by a /memreserve/ region in the device tree) polling their cpu-release-addr location, which must be contained in the reserved region. A wfe instruction may be inserted to reduce the overhead of the busy-loop and a sev will be issued by the primary CPU. When a read of the location pointed to by the - cpu-release-addr returns a non-zero value, the CPU must jump directly - to this value. + cpu-release-addr returns a non-zero value, the CPU must jump to this + value. The value will be written as a single 64-bit little-endian + value, so CPUs must convert the read value to their native endianness + before jumping to it. + +- CPUs with a "psci" enable method should remain outside of + the kernel (i.e. outside of the regions of memory described to the + kernel in the memory node, or in a reserved area of memory described + to the kernel by a /memreserve/ region in the device tree). The + kernel will issue CPU_ON calls as described in ARM document number ARM + DEN 0022A ("Power State Coordination Interface System Software on ARM + processors") to bring CPUs into the kernel. + + The device tree should contain a 'psci' node, as described in + Documentation/devicetree/bindings/arm/psci.txt. - Secondary CPU general-purpose register settings x0 = 0 (reserved for future use) diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt index 78a37712..5e054bf 100644 --- a/Documentation/arm64/memory.txt +++ b/Documentation/arm64/memory.txt @@ -21,7 +21,7 @@ The swapper_pgd_dir address is written to TTBR1 and never written to TTBR0. -AArch64 Linux memory layout: +AArch64 Linux memory layout with 4KB pages: Start End Size Use ----------------------------------------------------------------------- @@ -39,13 +39,38 @@ ffffffbffbc00000 ffffffbffbdfffff 2MB earlyprintk device ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O space -ffffffbbffff0000 ffffffbcffffffff ~2MB [guard] +ffffffbffbe10000 ffffffbcffffffff ~2MB [guard] ffffffbffc000000 ffffffbfffffffff 64MB modules ffffffc000000000 ffffffffffffffff 256GB kernel logical memory map +AArch64 Linux memory layout with 64KB pages: + +Start End Size Use +----------------------------------------------------------------------- +0000000000000000 000003ffffffffff 4TB user + +fffffc0000000000 fffffdfbfffeffff ~2TB vmalloc + +fffffdfbffff0000 fffffdfbffffffff 64KB [guard page] + +fffffdfc00000000 fffffdfdffffffff 8GB vmemmap + +fffffdfe00000000 fffffdfffbbfffff ~8GB [guard, future vmmemap] + +fffffdfffbc00000 fffffdfffbdfffff 2MB earlyprintk device + +fffffdfffbe00000 fffffdfffbe0ffff 64KB PCI I/O space + +fffffdfffbe10000 fffffdfffbffffff ~2MB [guard] + +fffffdfffc000000 fffffdffffffffff 64MB modules + +fffffe0000000000 ffffffffffffffff 2TB kernel logical memory map + + Translation table lookup with 4KB pages: +--------+--------+--------+--------+--------+--------+--------+--------+ |