diff options
author | Jaiprakash Singh <b44839@freescale.com> | 2014-10-07 05:23:14 (GMT) |
---|---|---|
committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:38:00 (GMT) |
commit | cd11c0ec055a21def103ee75812632e588b5fc0e (patch) | |
tree | 57c6148e72db937c48501ba84057b2c9eab0f873 /Documentation/devicetree | |
parent | 6962d5c31cf158ce11a10ea8e4a827e35302c563 (diff) | |
download | linux-fsl-qoriq-cd11c0ec055a21def103ee75812632e588b5fc0e.tar.xz |
IFC: Change IO accessor based on endianness
IFC registers can be of type Little Endian
or big Endian depending upon Freescale SoC.
Here SoC defines the register type of
IFC IP.So update accessors functions with
common IFC accessors functions to take
care both type of endianness.
IFC IO accressor are set at run time based
on IFC IP registers endianness.IFC node in
DTS file contains information about
endianness.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
---
This patch is under reviewing at url - https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg741449.html
Change-Id: Ib6d4669a94afa50e71ce522a008232fa21b0bc19
Reviewed-on: http://git.am.freescale.net:8181/20971
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt index d5e3704..ee6226b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt @@ -18,6 +18,8 @@ Properties: interrupt (NAND_EVTER_STAT). If there is only one, that interrupt reports both types of event. +- little-endian : If this property is absent, the big-endian mode will + be in use as default for registers. - ranges : Each range corresponds to a single chipselect, and covers the entire access window as configured. |