Make the diu driver work without board level initialization

So far the DIU driver does not have a mechanism to do the
board specific initialization. So on some platforms,
such as P1022, 8610 and 5121, The board specific initialization
is implmented in the platform file such p10222_ds.

Actually, the DIU is already intialized in the u-boot, the pin sharing
and the signal routing are also set in u-boot. So we can leverage that
in kernel driver to avoid board sepecific initialization, especially
for the corenet platform, which is the abstraction for serveral
platfroms.

The potential problem is that when the system wakeup from the deep
sleep, some platform settings may need to be re-initialized. The CPLD
and FPGA settings will be kept, but the pixel clock register which
usually locate at the global utility space need to be reinitialized.

Generally, the pixel clock setting was implemented in the platform
file, But the pixel clock register itself should be part of the DIU
module, And for P1022,8610 and T1040, the pixel clock register have the
same structure, So we can consider to move the pixel clock setting
from the platform to the diu driver. This patch provide the options
set the pixel clock in the diu driver. But the original platform pixel
clock setting stil can be used for P1022,8610 and 512x without any
update. To implement the pixel clock setting in the diu driver. the
following update in the diu dts node was needed.
display:display@180000 {
	compatible = "fsl,t1040-diu", "fsl,diu";
	-	reg = <0x180000 1000>;
	+	reg = <0x180000 1000 0xfc028 4>;
		pixclk = <0 255 0>;
 	interrupts = <74 2 0 0>;
	}

The 0xfc028 is the offset for pixel clock register. the 3 segment of
the pixclk stand for the PXCKDLYDIR, the max of PXCK and the
PXCKDLY which will be used by the pixel clock register setting.

This was tested on T1040 platform. For other platform, the original
node together with the platform settings still can work.

The binding update also included in this patch.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Change-Id: I0663914b08378fc7852eab788801f4e5dc59977d
Reviewed-on: http://git.am.freescale.net:8181/10327
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>

1 files changed, 15 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/diu.txt b/Documentation/devicetree/bindings/powerpc/fsl/diu.txt
index b66cb6d..fa902c8 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/diu.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/diu.txt
@@ -6,7 +6,11 @@ drive DVI monitors.
 Required properties:
 - compatible : should be "fsl,diu" or "fsl,mpc5121-diu".
 - reg : should contain at least address and length of the DIU register
-  set.
+  set. The address and length for pixel clock register is optional, it's
+  not needed for the platforms with the pixel clock setting function, such
+  as P1022, MPC8610, MPC5121; for the platform without clock setting function,
+  the pixel clock register and settings in 'pixclk' node work together to
+  provide the pixel clock setting in the diu driver.
 - interrupts : one DIU interrupt should be described here.
 - interrupt-parent : the phandle for the interrupt controller that
   services interrupts for this device.
@@ -15,6 +19,8 @@ Optional properties:
 - edid : verbatim EDID data block describing attached display.
   Data from the detailed timing descriptor will be used to
   program the display controller.
+- pixclk : the pixel clock register setting, includeing PXCKDLYDIR, PXCK
+  and PXCKDLY.
 
 Example (MPC8610HPCD):
 	display@2c000 {
@@ -32,3 +38,11 @@ Example for MPC5121:
 		interrupt-parent = <&ipic>;
 		edid = [edid-data];
 	};
+
+Example for T1040:
+	display:display@180000 {
+		compatible = "fsl,t1040-diu", "fsl,diu";
+		reg = <0x180000 1000 0xfc028 4>;
+		pixclk = <0 255 0>;
+		interrupts = <74 2 0 0>;
+	};