diff options
| author | Xiubo Li <Li.Xiubo@freescale.com> | 2014-08-19 04:38:03 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:36:39 (GMT) |
| commit | 15e87bc300c4ce9ebc1acc5627078eabd1e037f2 (patch) | |
| tree | 22023a419ce4dacb58b6d7da8fd87552ba209ad3 /Documentation | |
| parent | a6678fc8ee1624936f865ce4ee784f83a4428007 (diff) | |
| download | linux-fsl-qoriq-15e87bc300c4ce9ebc1acc5627078eabd1e037f2.tar.xz | |
pwm: fsl-ftm: Document 'big-endian' property
The same FTM PWM device can have a different endianness on different
SoCs. The device tree provides a property to describing this so that an
operating system device driver can handle all variants of the device.
Refer to the table below for the endianness of the FTM PWM block as
integrated into the existing SoCs:
SoC | FTM-PWM endianness
--------+-------------------
Vybrid | LE
LS1 | BE
LS2 | LE
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit a535e2e0debc2255fcf60a11d73fbb0534454cc3
Change-Id: Icf9f1efe7a4fd121cb5568f8552c01043110b108
Reviewed-on: http://git.am.freescale.net:8181/19867
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt index 0bda229..3899d6a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt @@ -1,5 +1,20 @@ Freescale FlexTimer Module (FTM) PWM controller +The same FTM PWM device can have a different endianness on different SoCs. The +device tree provides a property to describing this so that an operating system +device driver can handle all variants of the device. Refer to the table below +for the endianness of the FTM PWM block as integrated into the existing SoCs: + + SoC | FTM-PWM endianness + --------+------------------- + Vybrid | LE + LS1 | BE + LS2 | LE + +Please see ../regmap/regmap.txt for more detail about how to specify endian +modes in device tree. + + Required properties: - compatible: Should be "fsl,vf610-ftm-pwm". - reg: Physical base address and length of the controller's registers @@ -16,7 +31,8 @@ Required properties: - pinctrl-names: Must contain a "default" entry. - pinctrl-NNN: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. - +- big-endian: Boolean property, required if the FTM PWM registers use a big- + endian rather than little-endian layout. Example: @@ -32,4 +48,5 @@ pwm0: pwm@40038000 { <&clks VF610_CLK_FTM0_EXT_FIX_EN>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_1>; + big-endian; }; |