diff options
| author | Minghuan Lian <Minghuan.Lian@freescale.com> | 2014-11-10 10:05:39 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:40:37 (GMT) |
| commit | 1b706728df9fb41fdec5349526dca4ae6651af96 (patch) | |
| tree | 762f569272049474ea54fd1dddafa7451db3de56 /Documentation | |
| parent | fdb05ce37b6257faa22beb685f251ece9dd1400e (diff) | |
| download | linux-fsl-qoriq-1b706728df9fb41fdec5349526dca4ae6651af96.tar.xz | |
PCI: designware: Add support 4 ATUs assignment
Currently, pcie-designware.c only supports two ATUs, ATU0 is used
for CFG0 and MEM, ATU1 is used for CFG1 and IO. There is a conflict
when MEM and CFG0 are accessed simultaneously. The patch adds
'num-atus' property to PCIe dts node to describe the number of
PCIe controller's ATUs. If num_atus is bigger than or equal to 4,
we will change ATUs assignment: ATU0 for CFG0, ATU1 for CFG1,
ATU2 for MEM, ATU3 for IO.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
The patch is upstreaming
http://patchwork.ozlabs.org/patch/409170/
Change-Id: I317bf8a3648eafeb221da6479b7788de0028d8c5
Reviewed-on: http://git.am.freescale.net:8181/23496
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index e216af3..83ccba4 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -20,6 +20,7 @@ Required properties: numbers. - num-lanes: number of lanes to use - reset-gpio: gpio pin number of power good signal +- num-atus: number of ATUs. The default value is 2 if not present Example: |