ARM: ls1021a: add gating clocks to IP blocks.

A given application may not use all the peripherals on the device.
In this case, it may be desirable to disable unused peripherals.
DCFG provides a mechanism for gating clocks to IP blocks that are
not used when running an application.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>

---
This patch has been sent out to the community and under discussion：
URL：http://www.spinics.net/lists/arm-kernel/msg370133.html

Change-Id: Iedf07d12955b3fa011a0bef27236f73405cefb44
Reviewed-on: http://git.am.freescale.net:8181/21604
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/ls1021a-clock.txt b/Documentation/devicetree/bindings/clock/ls1021a-clock.txt
new file mode 100644
index 0000000..e53d976
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ls1021a-clock.txt
@@ -0,0 +1,27 @@
+Gating clock bindings for Freescale LS1021A SOC
+
+Required properties:
+- compatible:		Should be "fsl,ls1021a-gate"
+- reg:			Address and length of the register set
+- #clock-cells:		Should be <1>
+
+The clock consumers should specify the desired clock by having one clock
+ID in its "clocks" phandle cell.
+Please see include/dt-bindings/clock/ls1021a-clock.h for the full list of
+LS1021A clock IDs.
+
+Example:
+
+gate: gate@1ee0000 {
+	compatible = "fsl,ls1021a-gate";
+	reg = <0x0 0x1ee0000 0x0 0x10000>;
+	#clock-cells = <1>;
+};
+
+wdog0: wdog@2ad0000 {
+	compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt";
+	reg = <0x0 0x2ad0000 0x0 0x10000>;
+	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&gate LS1021A_CLK_WDOG12_EN>;
+	clock-names = "wdog12_en";
+};