dt-bindings: arm: add Freescale LS1021A SoC specific devict tree binding

Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index e935d7d..2e9b283 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -74,3 +74,31 @@ Required root node properties:
 i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
+
+
+------------------------------------------------
+
+Freescale LS1021A platfform device tree bindings
+------------------------------------------------
+
+Each device tree must specify the following compatible values:
+
+  "fsl,ls1021a"
+
+SoC-specific device tree bindings
+-------------------------------------------
+
+Each device tree must specify the following SoC-specific compatible values:
+
+  - compatible = "fsl,ls1021a-scfg":
+	scfg is the supplemental configuration unit, provides SoC specific
+	configuration and status registers for the chip.there isn't a dedicate
+	driver for it, device that has configuration and status register located
+	in this space can operate on it. Such as getting PEX port status.
+
+  - compatible = "fsl,ls1021a-dcfg":
+  	dcfg is the device configuration unit that provides general purpose
+	configuration and status for the device, there isn't a dedicate driver
+	for it, device that has configuration and status register located in
+	this space can operate on it. Such as setting the secondary core start
+	address and release the secondary core from holdoff and startup.