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| author | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 12:59:19 (GMT) |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 12:59:19 (GMT) |
| commit | 2f540738f8d228016c6cd0d3b303896c174ecee3 (patch) | |
| tree | 7e6574c041ac4386763f94d3d401d70f4ab6f55b /arch/arm/Kconfig | |
| parent | a3849a4c038a21075a0bc7eaf37f65a93976d10c (diff) | |
| parent | d8e9c00e38f6947cef7f5466a0a3d369461ab97f (diff) | |
| download | linux-fsl-qoriq-2f540738f8d228016c6cd0d3b303896c174ecee3.tar.xz | |
Merge branch 'tegra/cleanup' into next/cleanup
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2ad79b2..9277237 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1285,6 +1285,20 @@ config ARM_ERRATA_364296 processor into full low interrupt latency mode. ARM11MPCore is not affected. +config ARM_ERRATA_764369 + bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" + depends on CPU_V7 && SMP + help + This option enables the workaround for erratum 764369 + affecting Cortex-A9 MPCore with two or more processors (all + current revisions). Under certain timing circumstances, a data + cache line maintenance operation by MVA targeting an Inner + Shareable memory region may fail to proceed up to either the + Point of Coherency or to the Point of Unification of the + system. This workaround adds a DSB instruction before the + relevant cache maintenance functions and sets a specific bit + in the diagnostic control register of the SCU. + endmenu source "arch/arm/common/Kconfig" |