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| author | Thomas Gleixner <tglx@linutronix.de> | 2012-05-08 12:07:48 (GMT) |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2012-05-08 12:07:48 (GMT) |
| commit | 67ba5293f705eb1d1b98710e5ccb0f615936a6fc (patch) | |
| tree | cdb4cfd94033b5c0f42eeb4de368802049880a12 /arch/arm/Kconfig | |
| parent | 86627c93b35082f7a0e4d3111546943984b932c7 (diff) | |
| parent | d909a81b198a397593495508c4a5755fe95552fb (diff) | |
| download | linux-fsl-qoriq-67ba5293f705eb1d1b98710e5ccb0f615936a6fc.tar.xz | |
Merge branch 'smp/threadalloc' into smp/hotplug
Reason: Pull in the separate branch which was created so arch/tile can
base further work on it.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a3ad496..69145df 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1184,6 +1184,15 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_326103 + bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" + depends on CPU_V6 + help + Executing a SWP instruction to read-only memory does not set bit 11 + of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to + treat the access as a read, preventing a COW from occurring and + causing the faulting task to livelock. + config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" depends on CPU_V6 || CPU_V6K |