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| author | Dirk Behme <dirk.behme@de.bosch.com> | 2013-04-26 08:13:55 (GMT) |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-06-17 08:04:20 (GMT) |
| commit | 5a5ca56e057d206db13461b84a7da3a3543e1206 (patch) | |
| tree | 77aecfaf248bc4f2fe048e7a9ae1d51fd579cd18 /arch/arm/boot/dts/imx6qdl.dtsi | |
| parent | faacc290eeaf28f24a2ff5cb1ec033e6c9f3811d (diff) | |
| download | linux-fsl-qoriq-5a5ca56e057d206db13461b84a7da3a3543e1206.tar.xz | |
ARM: dts: i.MX6: configure L2 cache data and tag latency
Configure the data and tag latency for the L2 cache. This improves the
system performance.
This configuration is taken from Freescale's kernel patch
"ENGR00153601 [MX6]Adjust L2 cache parameter" [1]
which does
writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));
In this patch we are doing the same via the device tree.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 9e8296e..fd7cc6d 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -106,6 +106,8 @@ interrupts = <0 92 0x04>; cache-unified; cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; }; pmu { |