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authorDinh Nguyen <dinguyen@altera.com>2013-06-05 15:02:53 (GMT)
committerOlof Johansson <olof@lixom.net>2013-06-11 23:34:57 (GMT)
commit3d954cf1518f37edc0d5912d619bd0f644a27d7e (patch)
tree28d95bdbeee0160f8007689584afee337a1cc783 /arch/arm/boot/dts/socfpga_cyclone5.dts
parent6cd26ecedfa258369c2cd725cb33b0477ab2819b (diff)
downloadlinux-fsl-qoriq-3d954cf1518f37edc0d5912d619bd0f644a27d7e.tar.xz
ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Pavel Machek <pavel@denx.de> CC: <linux@arm.linux.org.uk> v2: - Moved "disabled" status to dtsi file Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_cyclone5.dts')
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dts13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958..973999d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
reg = <0x0 0x40000000>; /* 1GB */
};
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
soc {
clkmgr@ffd04000 {
clocks {
@@ -41,6 +48,12 @@
};
};
+ ethernet@ff702000 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+ status = "okay";
+ };
+
timer0@ffc08000 {
clock-frequency = <100000000>;
};