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author | Will Deacon <will.deacon@arm.com> | 2014-02-07 18:12:20 (GMT) |
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committer | Jiri Slaby <jslaby@suse.cz> | 2014-03-05 16:13:40 (GMT) |
commit | 160d1d210a8cc5b29722580484f5256882dc275e (patch) | |
tree | fafcf5df712f9b30ba01cd2a61a5d46a9f6981eb /arch/arm/include | |
parent | 751d789f6490b7c08ff49dae95509b2be29bac78 (diff) | |
download | linux-fsl-qoriq-160d1d210a8cc5b29722580484f5256882dc275e.tar.xz |
ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMU
commit bae0ca2bc550d1ec6a118fb8f2696f18c4da3d8e upstream.
During __v{6,7}_setup, we invalidate the TLBs since we are about to
enable the MMU on return to head.S. Unfortunately, without a subsequent
dsb instruction, the invalidation is not guaranteed to have completed by
the time we write to the sctlr, potentially exposing us to junk/stale
translations cached in the TLB.
This patch reworks the init functions so that the dsb used to ensure
completion of cache/predictor maintenance is also used to ensure
completion of the TLB invalidation.
Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'arch/arm/include')
0 files changed, 0 insertions, 0 deletions